LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
MPN: LTC2150CUJ-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $69.3 | $69.30 |
| 10 | $62.37 | $623.70 |
| 100 | $55.44 | $5,544.00 |
| 500 | $48.51 | $24,255.00 |
| 1,000 | $41.58 | $41,580.00 |
LTC2150CUJ-14 Overview
A pipelined ADC is a successive-stage converter that resolves the input sample through a cascade of low-resolution flash stages interleaved with sample-and-hold amplifiers; this architecture delivers high sample rates (hundreds of Msps) with low latency (five clock cycles here) and excellent dynamic linearity. Within the broader signal-chain taxonomy, the LTC2150CUJ-14 sits as ADC -> data converter -> signal-chain IC -> semiconductor, occupying the digitisation stage between an analog front end (AFE, amplifier or downconverter) and a digital processor (FPGA/DSP/ASIC).
Key headline parameters per the manufacturer datasheet 21521014fa: ±0.85 LSB typical INL, ±0.25 LSB typical DFL, no missing codes over temperature, 1.82 LSBRMS transition noise, 1.25 GHz full-power sample-and-hold bandwidth, and optional clock duty-cycle stabilizer for high performance across non-50% clock duty cycles. The differential ENC+/ENC- encode clock accepts sine, PECL, LVDS, TTL, or CMOS drivers, simplifying clocking from FPGA PLLs or crystal oscillators.
The part integrates a serial SPI port for per-channel configuration (output mode, test patterns, power modes), low-power Sleep and Nap modes for power-managed applications, and a pin-compatible 12-bit upgrade path (LTC2150-12 / LTC2151-14 / LTC2152-14 family) for code re-use across 12/14-bit and 170/210/250 Msps variants. Differential analog and clock inputs maximise second-order linearity and common-mode rejection.
Typical applications include cellular basestation receiver IF digitisation, medical imaging front ends (ultrasound beamformers, MRI receivers), radar and electronic-warfare IF sampling, cable-modem head-end CMTS downstream capture, broadband communications test equipment, and high-speed oscilloscope/data-acquisition front ends. Designers typically pair it with an AD8138 differential driver on the analog input, an AD9520 clock generator for ENC+, and an FPGA (e.g. Xilinx Kintex, Intel Cyclone) for LVDS capture.
When designing with the LTC2150CUJ-14, follow the layout guidelines in the evaluation board DC1565A-C: solid ground planes under the exposed pad, length-matched 50 Ω LVDS output traces, and 0.1 µF + 10 µF decoupling close to each supply pin. Power dissipation is roughly proportional to sample rate and output mode, so enable Nap or Sleep mode when the converter is idle to meet system power budgets.
This page synthesises distributor pricing, drop-in same-family alternatives, and practical design guidance that is not consolidated in the manufacturer datasheet.
Drop-in alternatives for LTC2150CUJ-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2150CUJ-14 (same form factor and footprint) — differing in Package, Sample Rate, Resolution, RoHS Status, Power-Saving Modes.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2150IUJ-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2150CUJ-14#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2150CUJ-14#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2151CUJ-14
✅ Drop-In✓ In Stock
$29.1 / Unit
View Datasheet →LTC2152CUJ-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2150CUJ-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 1 |
| Sample Rate | 170 Msps |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| INL (typical) | ±0.85 LSB |
| DNL (typical) | ±0.25 LSB |
| Transition Noise | 1.82 LSBRMS |
| Missing Codes | None over temperature |
| Full-Power Sample/Hold Bandwidth | 1.25 GHz |
| Digital Output Interface | DDR LVDS |
| Encode Clock Inputs | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) |
| Clock Duty-Cycle Stabilizer | Optional (selectable) |
| Configuration Interface | Serial SPI port |
| Latency | 5 clock cycles |
| Power-Saving Modes | Sleep and Nap modes |
| Package | 40-QFN (6 mm × 6 mm) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (Pb-free #PBF suffix) |
LTC2150CUJ-14 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | VA+ — Positive analog input (differential) |
| Pin 3 | VA- — Negative analog input (differential) |
| Pin 4 | REFTA — Top of reference ladder |
| Pin 5 | REFB — Bottom of reference ladder |
| Pin 6 | REFCM — Reference common-mode voltage |
| Pin 7 | SENSE — Reference programming pin (internal/external reference) |
| Pin 8 | GND — Ground reference |
| Pin 9 | VDD — Analog/digital 1.8 V supply |
| Pin 10 | GND — Ground reference |
| Pin 11 | OGND — Output driver ground |
| Pin 12 | OVDD — Output driver supply (1.8 V) |
| Pin 13 | OF+ — Output flag overrange positive |
| Pin 14 | OF- — Output flag overrange negative |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | D0-/D1+ — DDR LVDS output pair, bit 0 negative / bit 1 positive |
| Pin 17 | D0+/D1- — DDR LVDS output pair, bit 0 positive / bit 1 negative |
| Pin 18 | D2-/D3+ — DDR LVDS output pair, bit 2 negative / bit 3 positive |
| Pin 19 | D2+/D3- — DDR LVDS output pair, bit 2 positive / bit 3 negative |
| Pin 20 | D4-/D5+ — DDR LVDS output pair, bit 4 negative / bit 5 positive |
| Pin 21 | D4+/D5- — DDR LVDS output pair, bit 4 positive / bit 5 negative |
| Pin 22 | D6-/D7+ — DDR LVDS output pair, bit 6 negative / bit 7 positive |
| Pin 23 | D6+/D7- — DDR LVDS output pair, bit 6 positive / bit 7 negative |
| Pin 24 | D8-/D9+ — DDR LVDS output pair, bit 8 negative / bit 9 positive |
| Pin 25 | D8+/D9- — DDR LVDS output pair, bit 8 positive / bit 9 negative |
| Pin 26 | D10-/D11+ — DDR LVDS output pair, bit 10 negative / bit 11 positive |
| Pin 27 | D10+/D11- — DDR LVDS output pair, bit 10 positive / bit 11 negative |
| Pin 28 | D12-/D13+ — DDR LVDS output pair, bit 12 negative / bit 13 positive |
| Pin 29 | D12+/D13- — DDR LVDS output pair, bit 12 positive / bit 13 negative |
| Pin 30 | DCLK-/DCLK+ — DDR LVDS data-clock pair |
| Pin 31 | DCLK+/DCLK- — DDR LVDS data-clock pair (complementary) |
| Pin 32 | CS — SPI chip-select (active low) |
| Pin 33 | SCK — SPI serial clock |
| Pin 34 | SDI — SPI serial data input |
| Pin 35 | SDO — SPI serial data output |
| Pin 36 | MODE — Test-pattern / mode selection |
| Pin 37 | ENC+ — Positive encode clock input |
| Pin 38 | ENC- — Negative encode clock input |
| Pin 39 | GND — Ground reference |
| Pin 40 | VDD — Analog/digital 1.8 V supply |
Typical Applications
LTC2150CUJ-14 is suitable for 6 applications: Cellular Basestation Receiver IF Digitisation, Medical Imaging - Ultrasound Beamformer Front End, Radar and Electronic Warfare IF Sampling, Broadband Communications Test Equipment, High-Speed Data Acquisition / Oscilloscope Front End, Software Defined Radio (SDR) Wideband Capture.
Cellular Basestation Receiver IF Digitisation
The LTC2150CUJ-14 fits cellular basestation IF sampling because its 14-bit resolution and 170 Msps sample rate place the second- and third-Nyquist zones squarely within LTE and 5G NR IF band plans (typically 70-140 MHz). Its 1.25 GHz full-power sample/hold bandwidth captures the third-Nyquist zone cleanly without aliasing distortion. Per the manufacturer datasheet 21521014fa, ±0.85 LSB INL and 1.82 LSBRMS transition noise support the 70+ dB spurious-free dynamic range required by multi-carrier GSM/UMTS/LTE receivers. Designers pair the converter with an AD8138 differential driver on the analog input and an AD9520 jitter-cleaner on ENC+/ENC- for synchronised multi-channel diversity systems, before the DDR LVDS stream is deserialised inside a Xilinx Kintex or Intel Cyclone FPGA.
Recommended
Medical Imaging - Ultrasound Beamformer Front End
In ultrasound beamformer receivers the LTC2150CUJ-14's 14-bit / 170 Msps performance captures 40 MHz-bandwidth RF echoes with sufficient spurious-free dynamic range for tissue-harmonic imaging. Its 1.8 V single supply simplifies integration with portable battery-powered cart systems where low dissipation matters. The pipelined architecture's 5-clock-cycle latency is short enough for real-time beam-steering without introducing perceptible delay. Per Analog Devices datasheet 21521014fa, the differential analog input and differential ENC+/ENC- clock reject common-mode noise from switching power supplies in densely packed channel boards; multiple LTC2150CUJ-14s time-interleave under one FPGA for high-density 64- and 128-channel systems used in cart-based ultrasound.
Recommended
Radar and Electronic Warfare IF Sampling
The LTC2150CUJ-14 suits wideband radar and electronic-warfare IF sampling because its 1.25 GHz analog input bandwidth downconverts IF signals in the second or third Nyquist zone, reducing analog mixer stages and BOM cost. Per datasheet 21521014fa, 1.82 LSBRMS transition noise and ±0.85 LSB INL preserve the dynamic range needed to discriminate closely-spaced targets. The optional on-chip duty-cycle stabilizer maintains full performance even when the ENC+ source is a non-50%-duty-cycle VCO, simplifying synthesizer integration. Designers route the DDR LVDS outputs directly into an FPGA where digital downconversion extracts in-phase/quadrature baseband data for pulse compression.
Recommended
Broadband Communications Test Equipment
Automated test equipment for DOCSIS 3.1 cable-modem head-ends and broadband vector-signal analysers benefits from the LTC2150CUJ-14's 14-bit dynamic range and 170 Msps capture rate, which digitises wideband multi-carrier signals at baseband or low IF. The DDR LVDS interface streams samples directly into FPGA-based FFT processors for modulation-error-rate (MER) and adjacent-channel-power (ACP) measurements. Per Analog Devices datasheet 21521014fa, no-missing-codes operation over temperature simplifies calibration routines in production ATE. Sleep and Nap modes cut idle dissipation when the test set is between measurements, helping meet energy-efficiency targets in rack-mounted test platforms.
Recommended
High-Speed Data Acquisition / Oscilloscope Front End
The LTC2150CUJ-14 fits modular data-acquisition and oscilloscope front-end cards where 14-bit vertical resolution at 170 Msps extends usable bandwidth beyond typical 8-/10-bit scopes. Time-interleaving two or four converters under staggered clocks produces 340 Msps or 680 Msps aggregate sample rate while maintaining the same 1.8 V supply and DDR LVDS capture pattern, simplifying firmware across product tiers. Per datasheet 21521014fa, ±0.25 LSB DNL prevents sparkle codes in histogram measurements, critical for production-line test of mixed-signal ICs. The 40-QFN exposed pad provides low thermal resistance for densely packed multi-channel PCI Express cards used in laboratory and bench-top instruments.
Recommended
Software Defined Radio (SDR) Wideband Capture
The LTC2150CUJ-14 is well matched to wideband SDR receiver cards that digitise 0-100 MHz spectrum segments directly at the antenna, eliminating multiple analog downconversion stages. Its 14-bit resolution and 170 Msps sample rate deliver approximately 74 dB SNR at low input frequencies, supporting OFDM demodulation across Wi-Fi, LTE, and proprietary RF links in a single hardware platform. Per Analog Devices datasheet 21521014fa, differential analog inputs provide strong common-mode rejection, important when the converter shares a PCB with high-power RF front ends. The DDR LVDS output is captured by an FPGA that runs GNU-Radio-compatible signal-processing pipelines for spectrum analysis and demodulation.
Recommended
Recommended Products Summary
Engineering reference data for LTC2150CUJ-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2150IUJ-14 | LTC2150CUJ-14#PBF | LTC2150CUJ-14#TRPBF | LTC2151CUJ-14 | LTC2152CUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 170 Msps | 170 Msps | 170 Msps | 170 Msps | 210 Msps | 250 Msps |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Interface | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Pin Compatible Family | LTC2150-14 | LTC2150-14 | LTC2150-14 | LTC2150-14 | LTC2151-14 | LTC2152-14 |
Key Differentiators
- Pin-compatible 14-bit upgrade path within the LTC215x family at the same footprint (vs LTC2150IUJ-14)
- Lower power consumption than faster family members at the same resolution (vs LTC2152CUJ-14)
- Single 1.8 V supply simplifies FPGA interface versus older 3.3 V ADCs (vs Generic 3.3 V 14-bit ADC family (e.g. AD6645))
- On-chip clock duty-cycle stabilizer enables non-50%-duty clocks (vs Competing 14-bit ADCs without DCS)
Design Notes
Follow the DC1565A-C evaluation board layout: provide a solid uninterrupted ground plane on layer 2 beneath the 40-QFN exposed pad, length-match the DDR LVDS output pairs to within 0.5 mm, route the ENC+/ENC- differential encode clock as a 100 Ω differential pair, and place 0.1 µF + 10 µF decoupling capacitors within 3 mm of each supply pin. The exposed pad must be soldered to a continuous copper pour to meet the datasheet's thermal and ground-impedance specifications; unsoldered pads degrade sample-and-hold bandwidth and increase jitter.
Avoid driving ENC+/ENC- with a single-ended CMOS signal unless the unused input is AC-bypassed to ground; per datasheet 21521014fa the differential encode clock is the primary performance-defining input, and single-ended drive introduces harmonic distortion and degraded SNR. Similarly, do not leave the SENSE pin floating - tie SENSE to VDD through a 10 kΩ resistor for the internal 1.25 V reference, or to an external reference voltage for gain trim. Mis-terminated LVDS outputs cause reflection-induced sparkle codes in histograms.
Power dissipation scales roughly linearly with sample rate and output-driver activity. Estimated: at 170 Msps with DDR LVDS active, the LTC2150CUJ-14 dissipates approximately 250 mW from the 1.8 V analog and digital rails; enabling Nap mode drops consumption to ~30 mW and Sleep mode to <1 mW. Use a linear LDO (such as the Analog Devices ADP1741) rather than a switching regulator to power the analog rail, since the switching noise directly couples into the ADC and degrades SFDR.
Series-terminate each LVDS output pair at the ADC side with a 100 Ω resistor across the differential pair, and route each pair over a continuous reference plane with no splits. Match lengths within the pair to within 0.5 mm and keep total length under 50 mm to limit ISI at 170 Msps DDR. If routing to a distant FPGA, use an LVDS buffer (e.g. SN65LVDS387 or FIN1047) and place it within 25 mm of the ADC; long stub traces between ADC and FPGA cause reflections that show up as bit-error spurs in the captured spectrum.
Although the 40-QFN exposed pad keeps θJA low (approximately 30 °C/W on a 4-layer JEDEC PCB), operating at 170 Msps with continuous LVDS switching generates ~250 mW of dissipation (estimated) that must be sunk through the exposed pad to the ground-copper pour. For densely populated multi-channel boards (16+ channels), include thermal vias in a 4×4 array beneath the exposed pad and stitch the top-side copper to inner ground planes to keep junction temperature well below 125 °C for full-temperature-range operation.
Compliance Information
Pb-free #PBF / #TRPBF suffixes indicate RoHS-compliant lead-free terminations per Analog Devices nomenclature. AEC-Q100 not applicable - this is a commercial/industrial-grade converter not qualified for automotive applications.
