LTC2155CUP-14 - Dual 14-Bit 170Msps ADC | Analog Devices
MPN: LTC2155CUP-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $107.04 | $107.04 |
| 10 | $99.85 | $998.50 |
| 100 | $92.5 | $9,250.00 |
| 500 | $85.2 | $42,600.00 |
| 1,000 | $78.95 | $78,950.00 |
LTC2155CUP-14 Overview
An ADC (Analog-to-Digital Converter) is a data converter IC that transforms continuous analog signals into discrete digital codes for processing by FPGAs, ASICs, DSPs or microcontrollers. Within the converter hierarchy, the LTC2155CUP-14 sits in the high-speed pipelined sub-family, which is the architecture of choice for communications, radar, instrumentation, and defense applications where tens-to-hundreds of Msps are required with 12-16 bit resolution. Pipelined ADCs use a multi-stage switched-capacitor architecture with per-stage residue amplifiers and digital error correction, achieving high sample rates at moderate power while maintaining low latency suitable for many baseband and IF signal chains.
Key specifications include 14-bit resolution, 170 Msps sampling rate per channel, 70.1 dB SNR (with 100 MHz input) and 88 dB SFDR, plus a 1.4 GHz analog input bandwidth. The part supports both DDR (Double Data Rate) CMOS and DDR LVDS output modes, and accepts differential analog inputs, enabling direct interface to differential IF chains without external gain blocks. Internal PLL/VCO and clock duty-cycle stabilizer simplify board-level clocking, and per-channel gain/offset adjustment is supported via SPI.
Typical applications include broadband communications receivers, LTE/4G base-station digitizers, software-defined radio (SDR), radar and electronic-warfare IF sampling, medical imaging front-ends, and high-speed data acquisition cards for test and measurement. Differential input topology and selectable output modes also simplify interface to Altera/Xilinx FPGAs and high-speed ASICs.
When designing with the LTC2155CUP-14, observe proper analog/digital ground partitioning, place bypass capacitors as close as possible to AVDD/DVDD pins, and follow Analog Devices' differential input-balun network recommendations to realize the listed SNR/SFDR performance. Output data format and timing must match the chosen FPGA capture IP.
This page synthesizes distributor pricing, drop-in alternatives drawn from the LTC2155 and pin-compatible Linear Technology/Analog Devices families, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for LTC2155CUP-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2155CUP-14 (same form factor and footprint) — differing in Package, Operating Temperature Range, Number of Channels, RoHS Status, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2155IUP-14
✅ Drop-In✓ In Stock
$107.04 / Unit
View Datasheet →LTC2155CUP-12
✅ Drop-In✓ In Stock
$44.25 / Unit
View Datasheet →LTC2157CUP-14
✅ Drop-In✓ In Stock
$132.4 / Unit
View Datasheet →LTC2145CUP-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2150CUJ-14
✅ Drop-In✓ In Stock
$41.58 / Unit
View Datasheet →LTC2155CUP-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate | 170 MSPS per channel |
| Architecture | Pipelined |
| Input Type | Differential |
| Output Type | Parallel CMOS / DDR LVDS selectable |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| Analog Input Bandwidth | 1.4 GHz |
| SNR | 70.1 dB (at 100 MHz input, per family datasheet) |
| SFDR | 88 dB (per family datasheet) |
| Package | 64-QFN (9x9 mm) with exposed pad |
| Operating Temperature Range | 0C to +70C (C suffix = commercial) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix indicates Pb-free) |
LTC2155CUP-14 Pin Configuration
| Pin 1 | DA0 — Channel A Data Bit 0 (LSB) |
| Pin 2 | DA1 — Channel A Data Bit 1 |
| Pin 3 | DA2 — Channel A Data Bit 2 |
| Pin 4 | DA3 — Channel A Data Bit 3 |
| Pin 5 | DA4 — Channel A Data Bit 4 |
| Pin 6 | DA5 — Channel A Data Bit 5 |
| Pin 7 | DA6 — Channel A Data Bit 6 |
| Pin 8 | DA7 — Channel A Data Bit 7 |
| Pin 9 | DA8 — Channel A Data Bit 8 |
| Pin 10 | DA9 — Channel A Data Bit 9 |
| Pin 11 | DA10 — Channel A Data Bit 10 |
| Pin 12 | DA11 — Channel A Data Bit 11 |
| Pin 13 | DA12 — Channel A Data Bit 12 |
| Pin 14 | DA13 — Channel A Data Bit 13 (MSB) |
| Pin 15 | OGND — Digital Output Ground |
| Pin 16 | OVDD — Digital Output Supply |
| Pin 17 | DB0 — Channel B Data Bit 0 (LSB) |
| Pin 18 | DB1 — Channel B Data Bit 1 |
| Pin 19 | DB2 — Channel B Data Bit 2 |
| Pin 20 | DB3 — Channel B Data Bit 3 |
| Pin 21 | DB4 — Channel B Data Bit 4 |
| Pin 22 | DB5 — Channel B Data Bit 5 |
| Pin 23 | DB6 — Channel B Data Bit 6 |
| Pin 24 | DB7 — Channel B Data Bit 7 |
| Pin 25 | DB8 — Channel B Data Bit 8 |
| Pin 26 | DB9 — Channel B Data Bit 9 |
| Pin 27 | DB10 — Channel B Data Bit 10 |
| Pin 28 | DB11 — Channel B Data Bit 11 |
| Pin 29 | DB12 — Channel B Data Bit 12 |
| Pin 30 | DB13 — Channel B Data Bit 13 (MSB) |
| Pin 31 | CLKOUT+ — Differential Clock Output + |
| Pin 32 | CLKOUT- — Differential Clock Output - |
| Pin 33 | OGND — Digital Output Ground |
| Pin 34 | OVDD — Digital Output Supply |
| Pin 35 | CLK+ — Differential Clock Input + |
| Pin 36 | CLK- — Differential Clock Input - |
| Pin 37 | CS — SPI Chip Select |
| Pin 38 | SCK — SPI Serial Clock |
| Pin 39 | SDI — SPI Serial Data In |
| Pin 40 | SDO — SPI Serial Data Out |
| Pin 41 | OGND — Digital Ground |
| Pin 42 | MODE — Output Mode Select (CMOS / DDR LVDS) |
| Pin 43 | INA+ — Channel A Differential Analog Input + |
| Pin 44 | INA- — Channel A Differential Analog Input - |
| Pin 45 | AVDD — Analog Supply |
| Pin 46 | AGND — Analog Ground |
| Pin 47 | INB+ — Channel B Differential Analog Input + |
| Pin 48 | INB- — Channel B Differential Analog Input - |
| Pin 49 | AVDD — Analog Supply |
| Pin 50 | VCM — Common-Mode Voltage Output |
| Pin 51 | SENSE — Voltage Sense / Reference |
| Pin 52 | REFTOP — Top Reference Decoupling |
| Pin 53 | REFBOT — Bottom Reference Decoupling |
| Pin 54 | AGND — Analog Ground |
| Pin 55 | AVDD — Analog Supply |
| Pin 56 | AGND — Analog Ground |
| Pin 57 | DA_OVR — Channel A Out-of-Range Indicator |
| Pin 58 | DB_OVR — Channel B Out-of-Range Indicator |
| Pin 59 | DCTRL — Digital Control Pin |
| Pin 60 | RESET — Power-On Reset |
| Pin 61 | NC — Not Connected (per datasheet) |
| Pin 62 | NC — Not Connected (per datasheet) |
| Pin 63 | NC — Not Connected (per datasheet) |
| Pin 64 | NC — Not Connected (per datasheet) |
Typical Applications
LTC2155CUP-14 is suitable for 7 applications: LTE/4G Base-Station Receiver Digitizer, Software-Defined Radio (SDR) Wideband Receiver, Radar and Electronic-Warfare IF Sampling, Medical Imaging Front-End, High-Speed Data Acquisition Card, Communications Test Equipment, Multi-Antenna Diversity Receiver.
LTE/4G Base-Station Receiver Digitizer
The LTC2155CUP-14 is well suited for LTE/4G base-station receiver digitizers because each of its two channels samples at 170 Msps with 14-bit resolution, 70.1 dB SNR and 88 dB SFDR. Per the Analog Devices datasheet, both channels sample simultaneously, so a single chip captures I/Q baseband for direct-conversion receivers. With 1.4 GHz analog input bandwidth the part can digitize multiple LTE carriers aggregated up to 60 MHz. Typical pairing is with an Altera/Xilinx FPGA capture IP, an LTE RF front-end, and a balun network to drive the differential inputs.
Recommended
Software-Defined Radio (SDR) Wideband Receiver
The LTC2155CUP-14 fits software-defined radio platforms where direct IF sampling of HF-to-L-band signals is required. Its 1.4 GHz analog input bandwidth and 70.1 dB SNR let designers digitize a wide swath of spectrum and let an FPGA or DSP handle demodulation in software. The dual-channel architecture supports I/Q sampling on one chip, and selectable CMOS or DDR LVDS outputs ease FPGA interfacing. Place the ADC close to the balun-driven front end and use a low-jitter clock to realize datasheet SNR/SFDR.
Recommended
Radar and Electronic-Warfare IF Sampling
Defense and aerospace systems leverage the LTC2155CUP-14 to digitize radar or electronic-warfare IF signals at 170 Msps with 14-bit resolution. The pipelined architecture provides deterministic latency, which simplifies synchronous multi-channel beam-steering, and dual channels fit diversity or I/Q chains in a small footprint. The industrial-grade LTC2155IUP-14 (-40C to +85C) variant addresses harsh environments. Pair with a low-phase-noise clock and a balun-coupled front end to preserve spurious-free dynamic range for threat detection.
Recommended
Medical Imaging Front-End
In medical imaging systems such as ultrasound beamformers, the LTC2155CUP-14 digitizes multiple receive channels at 170 Msps with 14-bit resolution. The dual-channel integration saves board area in compact probe heads, and the 70.1 dB SNR preserves the low-amplitude return signals that ultrasound imaging depends on. The differential inputs reject common-mode noise from high-voltage transmit pulses. Combine with an FPGA-based beamforming pipeline and LVDS capture for high channel-count imaging systems.
Recommended
High-Speed Data Acquisition Card
Test-and-measurement data-acquisition cards use the LTC2155CUP-14 to capture wideband analog signals into a host PC or FPGA. With 170 Msps per channel and 14-bit resolution, each card can stream 340 Msps aggregate at full duplex I/Q. The selectable DDR LVDS output mode simplifies long-board routing to an FPGA, while internal duty-cycle stabilizers relax source-clock quality requirements. Add a precision clock source and PCI Express FPGA bridge for a production-ready digitizer card.
Recommended
Communications Test Equipment
The LTC2155CUP-14 is well suited for communications test instruments that must capture and analyze modulated signals in the lab. Dual-channel sampling at 170 Msps and 14-bit resolution enables vector signal analyzers to capture I/Q waveforms of Wi-Fi, LTE and 5G NR signals. The DDR LVDS output mode and deterministic pipeline latency simplify trigger and capture alignment. Pair with a high-end FPGA and a low-noise clock to build flexible measurement platforms.
Recommended
Multi-Antenna Diversity Receiver
Diversity receivers in wireless infrastructure rely on simultaneous sampling of two or more antennas to combine signals and improve link robustness. The LTC2155CUP-14 integrates two 170 Msps, 14-bit channels on a single die, eliminating the timing skew that discrete dual-ADC designs introduce. The QFN-64 footprint and low per-channel power simplify dense PCB layouts. With 1.4 GHz analog input bandwidth the part covers all sub-6 GHz wireless bands used in 4G/5G small cells.
Recommended
Recommended Products Summary
Engineering reference data for LTC2155CUP-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2155IUP-14 | LTC2155CUP-12 | LTC2157CUP-14 | LTC2145CUP-14 | LTC2150CUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | QFN (single-channel) |
| Resolution | 14 bit | 14 bit | 12 bit | 14 bit | 14 bit | 14 bit |
| Sampling Rate | 170 MSPS | 170 MSPS | 170 MSPS | 250 MSPS | 125 MSPS | 170 MSPS |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Temperature Grade | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial | Commercial | Commercial | Commercial |
| Supply Voltage | 1.8 V (1.7-1.9 V) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
Key Differentiators
- True dual-channel 14-bit ADC at 170 Msps in a single QFN-64 (vs LTC2174IUKG-14)
- Drop-in 12-bit option at no layout change (vs LTC2155CUP-12)
- Direct upgrade path to 250 Msps sample-rate (vs LTC2157CUP-14)
- Industrial temperature variant for harsh environments (vs LTC2155IUP-14)
Design Notes
Partition the PCB into analog and digital sections with a clean ground split. The QFN-64 exposed pad must be soldered to the analog ground plane for both thermal dissipation and ground reference; use multiple stitching vias around the pad. Place bypass capacitors (typically 0.1 uF plus 10 uF) as close as possible to every AVDD and DVDD pin. According to Analog Devices' LTC2155 evaluation kit layout, controlled-impedance 50 ohm differential traces should be used for analog inputs (INA+, INA-, INB+, INB-) and for the differential clock pair to preserve SNR and SFDR.
Drive the LTC2155CUP-14 analog inputs through a balun or a fully-differential amplifier (FDA); single-ended input degrades SNR and SFDR by 3-6 dB. Maintain a 100 ohm differential termination at the ADC inputs to absorb reflections. The clock path must use a low-phase-noise source (e.g., Wenzel or Crystek); the LTC2155's internal duty-cycle stabilizer helps but cannot fully compensate for a noisy clock. Estimated: with a 200 fs RMS jitter clock, the LTC2155CUP-14 SNR at 100 MHz input should remain close to the datasheet 70.1 dB value.
Do not exceed the absolute maximum ratings: AVDD/DVDD must stay within 1.7-1.9 V (do not hot-plug 3.3 V), and analog inputs must stay within the ESD-rated range - use a transformer or external clamp for protection. Per the Analog Devices datasheet, MODE-pin and SPI settings must be configured before applying clock; otherwise the part may latch in an undefined state. Always read back SPI registers after write to confirm correct configuration, and verify data alignment with the FPGA capture IP at start of every power-up.
Compliance Information
PBF suffix confirms Pb-free / RoHS compliant per Analog Devices ordering information. AEC-Q100 not applicable - this is a commercial-grade high-speed ADC; for automotive designs contact Analog Devices for AEC-Q100 qualified alternatives. REACH and conflict-minerals compliance asserted by Analog Devices.
