LTC2193IUKG - 16-Bit 80Msps Dual ADC, 76.8dB SNR | ADI
MPN: LTC2193IUKG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $119.74 | $119.74 |
| 10 | $107.77 | $1,077.70 |
| 100 | $95.79 | $9,579.00 |
| 500 | $86.23 | $43,115.00 |
| 1,000 | $78 | $78,000.00 |
LTC2193IUKG Overview
What is a high-speed dual ADC? A dual ADC is a single integrated circuit that contains two independent, simultaneously-sampling analog-to-digital converters sharing a common clock and reference. The 'simultaneous sampling' property preserves the phase relationship between the two analog inputs, which is critical in diversity receivers, MIMO wireless links, and I/Q demodulation paths. The 16-bit resolution provides 96 dB of dynamic range, placing dual ADCs in the signal chain hierarchy between front-end amplifiers/anti-alias filters and the digital baseband FPGA or ASIC.
Key features of the LTC2193IUKG include a single 1.8V analog supply, single 1.8V to 3.3V output supply, CMOS or DDR LVDS output modes, and pin-compatible scalability within the LTC2195/LTC2194/LTC2193 family (125/105/80 Msps). The pipelined architecture integrates a high-bandwidth differential sample-and-hold with on-chip voltage reference, while the data clock output simplifies FPGA capture. Its ultralow aperture jitter of 0.07 psRMS enables accurate undersampling of high-IF signals.
The LTC2193IUKG utilizes a 16-stage pipelined architecture with digital error correction. The wide input bandwidth supports IF sampling well above 100 MHz, and the configurable LVDS lane count (1-, 2-, or 4-bit-per-channel) allows designers to trade pin count for board complexity. The 'I' suffix denotes the industrial temperature grade of -40C to +85C, suitable for non-automotive commercial and industrial environments.
Typical applications include communications receivers, cellular base stations, smart antenna systems, handheld radio links, ultrasound and medical imaging, and portable instrumentation. In each of these, the simultaneous sampling and low power-to-performance ratio directly translate to reduced PCB area, longer battery life, or denser channel count.
When designing with this device, pay close attention to PCB layout: the analog and digital grounds should be separated and joined only at the exposed pad, and the input traces must be length-matched differential pairs to preserve SNR. Use the LTC217x/LTC219x family evaluation kit as a reference for the analog input network, clock distribution, and LVDS routing.
This page synthesizes distributor pricing, drop-in compatible alternatives from the same datasheet family, and practical PCB design notes not present on standard distributor listings, providing an engineer-focused decision brief for selecting the LTC2193IUKG.
Drop-in alternatives for LTC2193IUKG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2193IUKG (same form factor and footprint) — differing in Package, Resolution, Number of Channels, Input Type, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2191IUKG
✅ Drop-In✓ In Stock
$62.95 / Unit
View Datasheet →LTC2190IUKG
✅ Drop-In✓ In Stock
$18.21 / Unit
View Datasheet →LTC2184IUP
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$28.4 / Unit
View Datasheet →LTC2175IUKG-12
✅ Drop-In✓ In Stock
$28.1 / Unit
View Datasheet →LTC2171IUKG-12
✅ Drop-In✓ In Stock
$23.3 / Unit
View Datasheet →LTC2156IUP-14
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$134.1 / Unit
View Datasheet →LTC2193IUKG Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 80 Msps |
| Architecture | Pipelined |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 psRMS |
| Total Power Dissipation | 249 mW |
| Power per Channel | 125 mW |
| Analog Supply Voltage | 1.8 V |
| Output Supply Voltage | 1.8 V to 3.3 V |
| Output Interface | Serial LVDS (1, 2, or 4 bits per channel) |
| Input Type | Differential |
| Package | 52-pin QFN (7x8 mm) (UKG) |
| Operating Temperature | -40C to +85C (Industrial) |
| RoHS Status | Compliant |
LTC2193IUKG 52-pin qfn (7x8 mm) (ukg) Pin Configuration Guide
Pin configuration for LTC2193IUKG (52-pin qfn (7x8 mm) (ukg) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for LTC2193IUKG.
Refer to the datasheet for full pin configuration.
Typical Applications
LTC2193IUKG is suitable for 6 applications: Cellular Base Station Diversity Receiver, Handheld Radio Link IF Sampling, Ultrasound and Medical Imaging, Portable Test and Measurement Instrumentation, Smart Antenna Systems (Phased Arrays), Industrial Data Acquisition Systems.
Cellular Base Station Diversity Receiver
The LTC2193IUKG's dual simultaneous-sampling 16-bit channels are well matched to cellular base station diversity and MIMO receivers. Both antenna paths are digitized in phase-locked fashion, eliminating sample-to-sample skew that would otherwise corrupt the combining gain. At 80 Msps the part captures full UMTS and LTE carrier bandwidths with headroom for higher-order modulation, and the 76.8 dB SNR provides the noise floor required to resolve 64-QAM and 256-QAM constellations cleanly. The 249 mW total power dissipation is well within typical 4x4 MIMO thermal envelopes when four ADCs are deployed per radio. The 0.07 psRMS aperture jitter also enables clean digitizing of multicarrier GSM signals at high IF, removing the need for an external downconversion stage.
Recommended
Handheld Radio Link IF Sampling
In handheld software-defined radio links, the LTC2193IUKG digitizes directly at an IF center frequency, eliminating a complete analog downconversion stage. Its 0.07 psRMS aperture jitter keeps SNR degradation below 0.1 dB even at 140 MHz IF inputs, while the 76.8 dB SNR preserves link sensitivity. The 249 mW total dissipation is critical for battery-powered radios: two ADCs at this power allow over 8 hours of continuous operation on a single 18650 cell after the front-end LNA. The serial LVDS output mode (1, 2, or 4 bits per channel) lets designers trade FPGA pin count for board complexity. The industrial -40C to +85C temperature range covers outdoor and tactical radio deployments without thermal derating.
Recommended
Ultrasound and Medical Imaging
The LTC2193IUKG is well suited to portable ultrasound beamformer front-ends, where each transducer channel requires a precision 16-bit ADC. Simultaneous dual-channel sampling allows one ADC to handle two adjacent transducer elements, halving the per-channel PCB footprint and reducing cable harness complexity. The 76.8 dB SNR and 90 dB SFDR deliver the dynamic range required to resolve small specular reflectors alongside large anatomical structures, which is essential for diagnostic image quality. At 249 mW total power, the part supports battery-driven cart-based systems, while its 52-QFN 7x8 mm package enables dense channel arrays. The exposed thermal pad simplifies multi-ADC PCB thermal design in 64- and 128-channel systems.
Recommended
Portable Test and Measurement Instrumentation
Handheld spectrum analyzers and oscilloscope front-ends benefit from the LTC2193IUKG's 16-bit resolution and 80 Msps sample rate, which together provide the dynamic range and bandwidth needed to characterize signals from 1 kHz to 40 MHz without aliasing. The 90 dB SFDR ensures that harmonic and intermodulation measurements reflect the device under test rather than the digitizer. The 249 mW low power extends battery runtime for field engineers, while the small 52-QFN 7x8 mm package fits compact 1U/2U form factors. The configurable 1, 2, or 4 bits-per-channel LVDS output mode lets designers select the data rate that matches their FPGA fabric bandwidth, easing integration with low-cost Cyclone or Spartan-6 devices.
Recommended
Smart Antenna Systems (Phased Arrays)
In smart antenna and phased-array systems, the LTC2193IUKG provides the simultaneous dual-channel sampling needed to digitize paired antenna elements with strict phase coherence, which is required for accurate digital beamforming. The 0.07 psRMS aperture jitter preserves beam-pointing accuracy by minimizing sample-to-sample timing variation across the array, while the 76.8 dB SNR supports nulling of interferers in the spatial domain. The 80 Msps rate covers full cellular and Wi-Fi bandwidths per channel. The 52-QFN package and 249 mW power allow high channel-count arrays (32, 64, 128 elements) on standard FR-4 PCBs without exotic thermal management, simplifying deployment in 5G small-cell and satellite ground-station applications.
Recommended
Industrial Data Acquisition Systems
The LTC2193IUKG fits multi-channel industrial data acquisition systems where 16-bit resolution is needed for accurate sensor digitizing at moderate speeds. Its dual channel halves the per-channel cost and PCB area compared to using two single-channel ADCs, and the simultaneous sampling preserves phase relationships in vibration and acoustic monitoring. The 76.8 dB SNR captures low-level transducer signals (strain gauges, accelerometers) without missing fine detail, while the 80 Msps rate allows oversampling to push effective resolution past 16 bits through digital filtering. The industrial -40C to +85C temperature range supports factory-floor deployment, and the 1.8 V single supply simplifies power tree design in 24V-bus industrial systems.
Recommended
Recommended Products Summary
Engineering reference data for LTC2193IUKG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2191IUKG | LTC2190IUKG | LTC2184IUP | LTC2175IUKG-12 | LTC2171IUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UP) 7x8 mm - same outline | 52-QFN (UKG) 7x8 mm - same | 52-QFN (UKG) 7x8 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit | 12 bit |
| Sample Rate | 80 Msps | 80 Msps | 105 Msps | 105 Msps | 125 Msps | 125 Msps |
| SNR | 76.8 dB | 77.3 dB | 76.8 dB | 76.8 dB | 73.1 dB | 73.1 dB |
| Total Power | 249 mW | 249 mW | 360 mW | 360 mW | 360 mW | 300 mW |
| Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
Key Differentiators
- Highest SNR in the 80 Msps speed grade (vs LTC2171IUKG-12)
- Lower power than 105/125 Msps family members (vs LTC2190IUKG)
- Dual simultaneous sampling in a single package (vs Two single-channel ADCs)
Design Notes
Separate the analog and digital ground planes and join them only at the LTC2193IUKG's exposed thermal pad to avoid digital switching noise coupling into the analog input network. Route the differential AIN1+/AIN1- and AIN2+/AIN2- traces as length-matched 100 ohm differential pairs on the top layer, with no via transitions. Place the input RC network (typically 25 ohm series, 10 pF shunt to analog ground) within 5 mm of each input pin to preserve SNR.
The 80 Msps encode clock must be routed as a 50 ohm controlled-impedance trace with no stubs, and the clock source should have < 100 fs RMS jitter to avoid degrading the part's 0.07 psRMS aperture performance. Use an AD9516 or similar low-jitter clock buffer to fan out the system reference; avoid zero-delay clock splitters which add jitter. Keep the clock trace at least 3 mm away from the LVDS output pairs to prevent digital coupling back into the analog domain.
Do not omit the decoupling on the OVDD and AVDD pins: each AVDD pin requires a 1 uF ceramic plus a 100 nF high-frequency bypass placed within 2 mm of the pin. The reference decoupling (REF pin) is particularly critical - a missing 2.2 uF on this pin degrades linearity by several dB. Always use the #PBF suffix for lead-free / RoHS-compliant builds; the standard non-PBF parts use SnPb finish and may not be accepted by your contract manufacturer.
When using the 4-bit-per-channel LVDS mode, the data rate is 200 Msps per LVDS pair, which exceeds the capability of many low-cost FPGAs. The 1-bit-per-channel mode (DDR) reduces data rate to 80 Msps per pair and is widely supported. Estimate: at 80 Msps with 1-bit DDR LVDS, the FPGA must capture 160 Mbps per differential pair, which is comfortably within Spartan-6 and Cyclone IV capabilities without requiring SERDES blocks.
Compliance Information
RoHS compliant per #PBF suffix on the manufacturer part number. Industrial temperature grade -40C to +85C, not AEC-Q100 qualified. For automotive applications, consider the AEC-Q100 qualified ADC34J family from Texas Instruments or contact Analog Devices for automotive-grade dual ADC options.
