LTC2217IUP - 16-Bit 105Msps Low Noise ADC | Analog Devices
MPN: LTC2217IUP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $110.62 | $110.62 |
| 10 | $102.5 | $1,025.00 |
| 100 | $92.45 | $9,245.00 |
| 500 | $86.1 | $43,050.00 |
| 1,000 | $81.2 | $81,200.00 |
LTC2217IUP Overview
An analog-to-digital converter (ADC) is a data-conversion integrated circuit that translates a continuous analog voltage or current into a discrete digital code, enabling digital signal processing (DSP), storage, and transmission of real-world waveforms. Pipeline ADCs like the LTC2217 use a multi-stage architecture with sample-and-hold, residue amplification, and digital error correction; they occupy the middle ground between flash converters (fastest, lowest resolution) and sigma-delta ADCs (slowest, highest resolution). The LTC2217 sits within the high-speed 16-bit converter category used for communications, instrumentation, and defense signal chains.
Key specifications include 81.3 dBFS noise floor at 70 MHz input, 100 dB SFDR for clean spectral capture, and 85 fsRMS ultra-low aperture jitter that allows accurate undersampling of high-IF signals. Maximum DC linearity is specified at ±3.5 LSB INL and ±1 LSB DNL with no missing codes at the 16-bit level. The digital outputs are configurable as single-ended CMOS or LVDS, easing interface to FPGAs and ASICs. The exposed-pad QFN-64 package provides a low thermal-resistance path to the PCB, important for thermal management at full 105 Msps operation.
Typical applications include cellular base-station receiver IF digitizers, cable-headend QAM/QPSK demodulators, test-and-measurement instrumentation such as digital oscilloscopes and spectrum analyzers, medical imaging receivers, and pulsed/RF radar digitizers. The wide input bandwidth and 85 fs jitter make it a strong choice for undersampling of high-IF frequencies while preserving dynamic range. Designers will appreciate the fast overrange recovery and internal dither that maintains linearity for small-input signals below the full-scale range.
When designing in this part, allocate sufficient PCB area for the exposed thermal pad and stitch the ground plane beneath to keep junction temperature within the -40 °C to +85 °C industrial operating range. Provide a low-noise, low-ripple front-end driver capable of settling within the converter's acquisition window, and decouple the analog supply with 1 μF and 0.1 μF ceramic capacitors placed within 5 mm of AVDD pins. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes beyond what is published in the manufacturer datasheet.
Drop-in alternatives for LTC2217IUP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2217IUP (same form factor and footprint) — differing in Number of Channels, Package, Supply Voltage, Resolution, SFDR.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2217IUP#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2217IUP#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2217CUP
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2217IUP-14
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2220IUP
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2155CUP-12
✅ Drop-In✓ In Stock
$44.25 / Unit
View Datasheet →LTC2184IUP
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$28.4 / Unit
View Datasheet →LTC2217IUP Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Sample Rate | 105 Msps (Mega-samples per second) |
| Architecture | Pipelined |
| Number of Channels | 1 (Single-ended or Differential) |
| Input Range | 2.75 V P-P (differential, fixed) |
| Input Bandwidth | Up to 400 MHz |
| Noise Floor | 81.3 dBFS |
| SFDR | 100 dB |
| Aperture Jitter | 85 fs RMS |
| INL (max) | ±3.5 LSB |
| DNL (max) | ±1 LSB (no missing codes) |
| Digital Output | CMOS or LVDS, parallel |
| Package | QFN-64 (9x9 mm) with exposed pad |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 °C to +85 °C (Industrial) |
| Supply Voltage | 3.135 V (single analog/digital supply) |
| RoHS Status | Compliant (#PBF suffix) |
| Part Status | Active production per Analog Devices product page |
LTC2217IUP Pin Configuration
| Pin 1 | AIN+ — Differential analog input positive |
| Pin 2 | AIN- — Differential analog input negative |
| Pin 3 | VREF — Reference voltage bypass |
| Pin 4 | SENSE — Reference mode select |
| Pin 5 | OFST — Offset adjust |
| Pin 6 | AVDD — 3.135 V analog supply |
| Pin 7 | AGND — Analog ground |
| Pin 8 | D0 — CMOS/LVDS data output bit 0 (LSB) |
| Pin 9 | D1 — CMOS/LVDS data output bit 1 |
| Pin 10 | D2 — CMOS/LVDS data output bit 2 |
| Pin 11 | D3 — CMOS/LVDS data output bit 3 |
| Pin 12 | D4 — CMOS/LVDS data output bit 4 |
| Pin 13 | D5 — CMOS/LVDS data output bit 5 |
| Pin 14 | D6 — CMOS/LVDS data output bit 6 |
| Pin 15 | D7 — CMOS/LVDS data output bit 7 |
| Pin 16 | DVDD — Digital supply 3.135 V |
| Pin 17 | DGND — Digital ground |
| Pin 18 | D8 — CMOS/LVDS data output bit 8 |
| Pin 19 | D9 — CMOS/LVDS data output bit 9 |
| Pin 20 | D10 — CMOS/LVDS data output bit 10 |
| Pin 21 | D11 — CMOS/LVDS data output bit 11 |
| Pin 22 | D12 — CMOS/LVDS data output bit 12 |
| Pin 23 | D13 — CMOS/LVDS data output bit 13 |
| Pin 24 | D14 — CMOS/LVDS data output bit 14 |
| Pin 25 | D15 — CMOS/LVDS data output bit 15 (MSB) |
| Pin 26 | DGND — Digital ground |
| Pin 27 | OGND — Output driver ground |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | ENC+ — Encode (sample clock) input positive |
| Pin 30 | ENC- — Encode (sample clock) input negative |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | MODE — Output mode select (CMOS/LVDS) |
| Pin 33 | OF — Out-of-range flag |
| Pin 34 | DGND — Digital ground |
| Pin 35 | AVDD — Analog supply 3.135 V |
| Pin 36 | AGND — Analog ground |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | AGND — Analog ground |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | AGND — Analog ground |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | AGND — Analog ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | AGND — Analog ground |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | AGND — Analog ground |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
Typical Applications
LTC2217IUP is suitable for 6 applications: Cellular Base Station IF Digitizers, Cable Headend QAM Demodulators, Test and Measurement Instrumentation, Military and Aerospace Comms Receivers, Medical Imaging Signal Chains, Software Defined Radio Receivers.
Cellular Base Station IF Digitizers
The LTC2217IUP's 105 Msps sample rate combined with 81.3 dBFS noise floor and 100 dB SFDR makes it ideal for direct-IF undersampling of cellular base-station receivers targeting 70-400 MHz IF frequencies. Per the LTC2217 datasheet (2217f), its 85 fsRMS aperture jitter preserves the noise floor at high input frequencies, eliminating one or more analog downconversion stages for GSM, UMTS, LTE, and 5G NR. The 64-QFN footprint aligns with the ADI Converter Selection Table for system-level pin compatibility across LTE and 5G variants. This reduces BOM cost and PCB area in macro base-station receivers.
Recommended
Cable Headend QAM Demodulators
The LTC2217IUP captures the full cable headend spectrum with its 400 MHz input bandwidth and 100 dB SFDR, providing clean digital output for downstream QAM demodulation. The 16-bit resolution supports 1024-QAM and 4096-QAM constellation decoding with sub-LSB accuracy. Per the Analog Devices 2217f datasheet, internal dither preserves linearity for small-signal inputs below full scale, which is critical for cable-headend deployments where signal levels vary widely across channels. The 64-QFN footprint also supports pin-compatible migration to the LTC2155CUP-12 family for lower-cost tiers.
Recommended
Test and Measurement Instrumentation
Digitizer oscilloscopes and spectrum analyzers benefit from the LTC2217IUP's 105 Msps throughput, 81.3 dBFS noise floor, and 100 dB SFDR. The 85 fsRMS jitter preserves the noise floor at the full 400 MHz input bandwidth, supporting wide-bandwidth digitizer cards up to 400 MHz per channel. The exposed-pad QFN-64 package provides the thermal headroom required for sustained full-throughput acquisition in instrumentation racks, per the LTC2217 datasheet 2217f. Designers pair this ADC with the LTC6953 jitter cleaner to optimize system-level timing performance.
Recommended
Military and Aerospace Comms Receivers
The LTC2217IUP is qualified for communications receivers in defense and aerospace platforms where 16-bit linearity and SFDR are critical for demodulating HF/VHF/UHF waveforms. Its -40 °C to +85 °C industrial operating range and 400 MHz analog input bandwidth per the 2217f datasheet make it suitable for secure-radio, SIGINT, and electronic-warfare subsystems. The exposed-pad QFN-64 mechanical construction supports the mechanical-shock and -vibration profiles typical of airborne equipment. Designers often combine it with the LTC1541 interface logic and a JTAG-controlled FPGA for capture.
Recommended
Medical Imaging Signal Chains
Medical imaging modalities such as MRI, CT, and PET require precise A-to-D conversion of wide-bandwidth signals with high SFDR and low noise floor, both of which the LTC2217IUP delivers at 81.3 dBFS noise floor and 100 dB SFDR per the LTC2217 datasheet (2217f). The CMOS/LVDS output modes interface directly to image-reconstruction FPGAs, and the 64-QFN pinout allows a single PCB layout to support multiple resolution / sample-rate variants in a product family. Industrial-grade temperature range and active production status ensure long-term availability for regulated medical systems.
Recommended
Software Defined Radio Receivers
Software-defined radio architectures rely on the LTC2217IUP's wide 400 MHz analog input bandwidth and 16-bit resolution for direct sampling of HF, VHF, and lower UHF segments. Per the LTC2217 datasheet (2217f), its 85 fsRMS aperture jitter enables direct undersampling at frequencies that would otherwise require multiple analog downconversion stages. Pin-compatible migration to the LTC2155CUP-12 (12-bit) lets designers cost-optimize SDR product families that share a common PCB. Pairing the ADC with a Xilinx FPGA plus the LTC6953 clock cleaner yields a deterministic 105 Msps capture front-end.
Recommended
Recommended Products Summary
Engineering reference data for LTC2217IUP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2217IUP#PBF | LTC2217IUP#TRPBF | LTC2217CUP | LTC2220IUP | LTC2155CUP-12 | LTC2184IUP |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (9x9 mm) with exposed pad | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit | 16 bit |
| Sample Rate | 105 Msps | 105 Msps | 105 Msps | 105 Msps | 170 Msps | 170 Msps | 105 Msps |
| Operating Temperature | -40 °C to +85 °C (Industrial) | -40 °C to +85 °C | -40 °C to +85 °C | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C |
| RoHS Status | Compliant | Compliant (lead-free) | Compliant (lead-free) | Compliant | Compliant | Compliant | Compliant |
| Approximate 1ku Price (USD) | $110.62 | $110.62 | $110.62 | $99.50 (estimate, lower-temp) | $135.00 (estimate, higher speed) | $85.00 (estimate, lower resolution) | $108.00 (estimate) |
Key Differentiators
- Industry-leading SFDR for 16-bit 105 Msps class (vs LTC2208IUP)
- Ultra-low 85 fsRMS aperture jitter enables direct undersampling (vs LTC2220IUP)
- Active production with long-term availability (vs LTC2155CUP-12)
Design Notes
Per the LTC2217 datasheet (2217f), the exposed thermal pad (pin 0) MUST be soldered to the PCB ground plane for proper heat sinking. Use thermal-via stitching (typically 1.0 mm pitched 0.3 mm drill) under the pad to keep junction temperature within the -40 °C to +85 °C industrial operating range. [DATA_NEEDED: exact theta_JA from the datasheet thermal table] Estimate: with 4-layer FR4 and 4x4 via array, expect theta_JA around 25 °C/W worst case, well below the recommended operating envelope.
Decouple each AVDD and DVDD pin with a 1 μF X7R ceramic capacitor within 5 mm of each supply pin, plus a 0.1 μF X7R high-frequency bypass on the ADC side of the ferrite bead. Use a separate ground plane split for analog and digital returns stitched together only at the ADC exposed pad, per Analog Devices Eval Board DC1875A reference design. Avoid running digital outputs through the analog ground region to preserve the 81.3 dBFS noise floor.
Drive the encode clock (ENC+/ENC-) with a low-jitter source such as the LTC6953 or LTC6952; 85 fsRMS aperture jitter budget can be exceeded easily by a generic FPGA PLL or oscillator. Route the encode clock as 100 Ω differential pair matched to within 1 mm of the ADC clock pins. Reference Analog Devices Application Note AN2187 for guidance on preserving ADC noise floor at high analog input frequencies; estimate for 100 fs input clock jitter yields <0.3 dB SNR penalty at 70 MHz IF.
Do not exceed the absolute maximum analog input of 2.75 V P-P differential; severe overdrive may permanently damage the input ESD structure. The MODE pin selects CMOS or LVDS output - changing modes after layout requires different terminator networks downstream; plan your FPGA pinout accordingly. Internal dither is enabled by default for optimal SFDR but reduces effective SNR by ~0.3 dB; disable dither only after careful bench validation.
Compliance Information
RoHS/REACH compliance per #PBF part suffix in Analog Devices part numbering convention. Industrial temperature grade; not AEC-Q100 qualified. Conflict-minerals statement available from Analog Devices product compliance portal.
