LTC2267CUJ-14 - 14-Bit 105Msps Dual ADC, Serial LVDS | ADI
MPN: LTC2267CUJ-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.31 | $68.31 |
| 10 | $61.48 | $614.80 |
| 100 | $54.65 | $5,465.00 |
| 500 | $47.82 | $23,910.00 |
| 1,000 | $40.99 | $40,990.00 |
LTC2267CUJ-14 Overview
What is a pipelined dual ADC? A pipelined ADC is the dominant converter architecture for sample rates from about 10 Msps to several hundred Msps. It uses multiple low-resolution stages to digitize the input, with each stage driving the next while the previous sample is being held; this parallelism achieves high throughput while keeping per-stage accuracy modest. Dual (2-channel) variants integrate two such pipelines on one die with shared clocking, enabling simultaneous sampling of I/Q or two sensor channels. ADCs are part of the broader data-converter hierarchy: data converter -> ADC -> high-speed ADC -> pipelined ADC. Compared with SAR or sigma-delta types, pipelined ADCs sacrifice latency and per-sample settling in exchange for the highest sustained conversion rates at moderate (10-16 bit) resolution.
Key features of the LTC2267CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and 1.2 LSB RMS transition noise. Each channel outputs data over two LVDS lanes (2-lane mode), with a 1-lane option available at lower sampling rates to reduce board routing complexity. Serialization is selectable at 16-, 14-, or 12-bit widths, and the device includes an 800 MHz full-power sample-and-hold amplifier, shutdown and nap power modes, and a serial SPI port for configuration.
The architecture is based on a switched-capacitor pipeline with proprietary calibration logic that trims capacitor mismatch at power-up and on demand. The high-bandwidth track-and-hold front-end preserves signal integrity for IF-sampling receivers, while the low-jitter clock-recovery-friendly LVDS interface simplifies FPGA/ASIC interconnect. Per-channel power is approximately 135 mW at 105 Msps, dropping further in nap and shutdown states.
Typical applications include cellular base-station receivers, software-defined radio, radar and lidar digitizers, medical imaging, and portable test instrumentation. The wide input bandwidth also enables direct IF sampling, removing a mixer stage in many receiver chains. The device is pin-compatible with the 14-bit and 12-bit versions in Analog Devices' LTC226x family, enabling a single PCB to support multiple resolutions.
When designing with the LTC2267CUJ-14, allocate a quiet analog ground plane under the package and route the LVDS pairs as 100-ohm differential microstrip. A low-jitter clock (>100 fs rms jitter) is required to preserve SNR at high input frequencies; follow the datasheet reference decoupling scheme exactly. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical layout notes that go beyond the datasheet.
Drop-in alternatives for LTC2267CUJ-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2267CUJ-14 (same form factor and footprint) — differing in Package, RoHS Status, Input Type, Resolution, Sample Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2267IUJ-14
✅ Drop-In✓ In Stock
$31.2 / Unit
View Datasheet →LTC2267CUJ-14#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2267CUJ-14#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2268IUJ-14
✅ Drop-In✓ In Stock
$72 / Unit
View Datasheet →LTC2266IUJ-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2151CUJ-14
✅ Drop-In✓ In Stock
$29.1 / Unit
View Datasheet →LTC2267CUJ-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 105 Msps |
| Architecture | Pipelined |
| Input Type | Differential, with 800 MHz full-power bandwidth S/H |
| INL | ±1 LSB (typical) |
| DNL | ±0.3 LSB (typical) |
| Missing Codes | None over temperature |
| Transition Noise | 1.2 LSB RMS |
| SNR | 73.4 dB |
| SFDR | 85 dB |
| Digital Output | Serial LVDS, 2-lane (or 1-lane at lower rates) |
| Serialization Width | 16-, 14-, or 12-bit selectable |
| Power per Channel | Approximately 135 mW at 105 Msps |
| Power Modes | Active, Nap, Shutdown |
| Configuration Interface | Serial SPI port |
| Operating Temperature | 0°C to +70°C (commercial, C-grade) |
| Package | 40-pin QFN (6mm × 6mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (#PBF suffix) |
| Lead-Free | Yes |
| MSL Level | 1 |
| Pin Compatibility | Pin-compatible with 14-bit and 12-bit LTC226x family variants |
LTC2267CUJ-14 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | VAIN1+ — Channel 1 analog input, positive |
| Pin 3 | VAIN1- — Channel 1 analog input, negative |
| Pin 4 | GND — Ground reference |
| Pin 5 | VAIN2+ — Channel 2 analog input, positive |
| Pin 6 | VAIN2- — Channel 2 analog input, negative |
| Pin 7 | GND — Ground reference |
| Pin 8 | REF — Internal reference bypass |
| Pin 9 | SENSE — Reference mode select |
| Pin 10 | GND — Ground reference |
| Pin 11 | VCM — Common-mode voltage output |
| Pin 12 | OGND — Output driver ground |
| Pin 13 | VDD — Analog supply |
| Pin 14 | OVDD — Output driver supply |
| Pin 15 | OGND — Output driver ground |
| Pin 16 | CLK+ — Differential clock input, positive |
| Pin 17 | CLK- — Differential clock input, negative |
| Pin 18 | GND — Ground reference |
| Pin 19 | ENC+ — Encoded LVDS output lane A, positive |
| Pin 20 | ENC- — Encoded LVDS output lane A, negative |
| Pin 21 | FR+ — Frame LVDS output, positive |
| Pin 22 | FR- — Frame LVDS output, negative |
| Pin 23 | GND — Ground reference |
| Pin 24 | OVDD — Output driver supply |
| Pin 25 | OGND — Output driver ground |
| Pin 26 | DOUT1A+ — Channel 1 LVDS data output lane A, positive |
| Pin 27 | DOUT1A- — Channel 1 LVDS data output lane A, negative |
| Pin 28 | DOUT1B+ — Channel 1 LVDS data output lane B, positive |
| Pin 29 | DOUT1B- — Channel 1 LVDS data output lane B, negative |
| Pin 30 | OGND — Output driver ground |
| Pin 31 | OVDD — Output driver supply |
| Pin 32 | DOUT2A+ — Channel 2 LVDS data output lane A, positive |
| Pin 33 | DOUT2A- — Channel 2 LVDS data output lane A, negative |
| Pin 34 | DOUT2B+ — Channel 2 LVDS data output lane B, positive |
| Pin 35 | DOUT2B- — Channel 2 LVDS data output lane B, negative |
| Pin 36 | OGND — Output driver ground |
| Pin 37 | SDI — SPI serial data input |
| Pin 38 | SCK — SPI serial clock |
| Pin 39 | CS — SPI chip select (active low) |
| Pin 40 | SDO — SPI serial data output |
Typical Applications
LTC2267CUJ-14 is suitable for 6 applications: Cellular Base-Station Receiver, Software-Defined Radio (SDR), Radar and Lidar Digitizer, Medical Imaging Front-End, Portable Test Instrumentation, Industrial Non-Destructive Testing.
Cellular Base-Station Receiver
The LTC2267CUJ-14's 105 Msps dual channels and 73.4 dB SNR make it well suited to digitizing intermediate-frequency (IF) signals in cellular base-station receivers. The 14-bit resolution preserves the wide dynamic range needed for multi-carrier GSM/LTE capture while the dual channels enable simultaneous diversity or main/diversity reception from a single IC. The 800 MHz full-power sample-and-hold bandwidth permits direct IF sampling up to roughly 200 MHz, removing an external mixer stage. The serial LVDS interface minimizes pin count on the FPGA interconnect, and the LVDS common-mode is FPGA-ASIC friendly. Nap and shutdown modes support duty-cycled TDD-LTE frames.
Recommended
Software-Defined Radio (SDR)
Software-defined radio platforms benefit from the LTC2267CUJ-14's wide analog input bandwidth, dual simultaneous channels (for I/Q sampling), and serial LVDS that drops cleanly into an FPGA fabric. The 105 Msps rate captures full-bandwidth signals up to about 40 MHz Nyquist, sufficient for many wideband receivers including 2G/3G cellular, DAB, and some Wi-Fi preamble paths. The dual ADC allows direct sampling of I and Q baseband signals from a quadrature demodulator, halving the FPGA sample rate. SPI configuration lets the same hardware support multiple decimation and bandwidth modes. Nap mode is useful for battery-powered field SDRs between active transmissions.
Recommended
Radar and Lidar Digitizer
Pulsed radar and lidar receivers require fast, high-resolution digitizers that can capture the full return pulse shape. The LTC2267CUJ-14's 14-bit resolution and 105 Msps per-channel sampling preserve pulse amplitude fidelity, while the 73.4 dB SNR keeps the noise floor well below typical return-signal levels. Dual channels allow simultaneous sampling of two receiver antennas, supporting monopulse angle estimation in radar or quadrature lidar detection schemes. The 800 MHz input bandwidth handles wideband FMCW chirps without aliasing. Nap and shutdown modes let pulsed systems idle between emissions, cutting average power in high-duty-cycle radar. The 40-QFN thermal performance supports continuous receive operation in compact enclosures.
Recommended
Medical Imaging Front-End
Ultrasound and other medical imaging systems stack 32-128 receive channels, each demanding high dynamic range and small footprint. The LTC2267CUJ-14's dual-channel integration halves the per-channel board area versus single-channel ADCs, while 14-bit resolution at 105 Msps captures the full echo bandwidth for harmonic and Doppler modes. The 85 dB SFDR is sufficient for low-contrast tissue differentiation, and the 73.4 dB SNR keeps the noise floor below clinically meaningful echo amplitudes. Shutdown mode supports battery-powered portable ultrasound carts. The 40-QFN exposed pad simplifies thermal management across the densely packed probe-head PCB. SPI configurability enables beam-former specific timing across channels.
Recommended
Portable Test Instrumentation
Handheld oscilloscopes, spectrum analyzers, and signal analyzers demand small, low-power ADCs with high dynamic performance. The LTC2267CUJ-14's dual channels and 105 Msps rate let a compact design offer two simultaneous input ranges (e.g., 50 ohm and 1 Mohm) or true differential inputs without stacking two ADCs. Nap and shutdown modes reduce idle current between triggered captures, extending battery life in field instruments. The 14-bit resolution and 73.4 dB SNR are adequate for general-purpose benchtop accuracy. The 40-QFN 6x6 mm footprint leaves ample board area for analog front-end conditioning and FPGA DSP blocks. SPI configuration supports per-test-mode gain and offset calibration.
Recommended
Industrial Non-Destructive Testing
Ultrasonic flaw detection, eddy-current testing, and acoustic-emission monitoring all rely on wideband, high-dynamic-range digitizers. The LTC2267CUJ-14's 14-bit resolution at 105 Msps preserves the amplitude fidelity required for crack-sizing algorithms, while the dual channels support transmit/receive or two-probe configurations in a single IC. The 800 MHz input bandwidth captures high-frequency transducer harmonics, and the 1.2 LSB RMS transition noise keeps measurement uncertainty low. Industrial-temperature variants (-40C to +85C) such as the LTC2267IUJ-14 extend usability to harsh factory environments. Nap mode supports battery-powered portable NDT scanners between inspections.
Recommended
Recommended Products Summary
Engineering reference data for LTC2267CUJ-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2267IUJ-14 | LTC2268IUJ-14 | LTC2266IUJ-14 | LTC2151CUJ-14 |
|---|---|---|---|---|---|
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 105 Msps | 105 Msps | 125 Msps | 80 Msps | Lower speed grade |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature | 0°C to +70°C (C grade) | -40°C to +85°C (I grade) | -40°C to +85°C (I grade) | -40°C to +85°C (I grade) | 0°C to +70°C (C grade) |
| Digital Output | Serial LVDS, 2-lane | Serial LVDS, 2-lane | Serial LVDS, 2-lane | Serial LVDS, 2-lane | Serial LVDS |
| Approx. Power at Full Speed | 270 mW total | 270 mW total | 320 mW total | 210 mW total | Lower |
| RoHS / Lead-Free | Yes (#PBF suffix) | Yes (#PBF suffix) | Yes (#PBF suffix) | Yes (#PBF suffix) | Yes (#PBF suffix) |
Key Differentiators
- Dual simultaneous sampling in a single 40-QFN (vs LTC2204IUK#PBF (single-channel 14-bit ADC))
- Pin-compatible speed options across the LTC226x family (vs LTC2268IUJ-14 (125 Msps) and LTC2266IUJ-14 (80 Msps))
- Wide S/H bandwidth enables direct IF sampling (vs Discrete mixer + IF-ADC chain)
Design Notes
Use a continuous, unbroken analog ground plane under the LTC2267CUJ-14 and route the LVDS pairs as 100-ohm differential microstrip over a solid ground reference. Keep the analog input traces strictly symmetrical: a 0.5 mm mismatch between AIN+ and AIN- paths degrades even-order distortion. Place the differential input coupling network (typically two 33 ohm resistors and shunt caps) within 5 mm of the input pins.
Clock jitter dominates SNR at high input frequencies. The LTC2267CUJ-14 requires a sampling clock with <100 fs rms jitter to preserve its 73.4 dB SNR at 100 MHz input; a low-jitter clock generator such as AD9523-1 is suggested. The CLK+/CLK- pair must be AC-coupled and routed as a 100-ohm differential pair; do not share ground returns with the analog input traces. Estimated: 1 ps of additional clock jitter degrades SNR by approximately 20*log10(1/(2*pi*fin*sigma_jitter)) dB at the target input frequency.
The 40-QFN exposed pad is the primary thermal path. Solder it to a 6x6 mm copper pour on the top layer and stitch it down with at least 9 thermal vias to an internal ground plane. Estimated: at 270 mW total dissipation and theta_JA 32 C/W on a 4-layer JEDEC test board, junction rises roughly 9C above ambient - well within the 0C to +70C commercial rating without a heatsink.
Do not float SENSE or REF pins; they configure internal reference modes. Leaving SENSE open disables the on-chip reference and prevents startup. Tie unused LVDS output lanes (1-lane mode) to OGND through 100-ohm termination rather than leaving them floating, to avoid crosstalk into active lanes. Always run the on-chip calibration sequence at power-up via the SPI port before sampling valid data.
Compliance Information
RoHS-compliant per #PBF suffix; lead-free and Pb-free terminal finish. Industrial-grade variants (IUJ-14 suffix) are not AEC-Q100 qualified; AEC-Q100 is not applicable for this converter family.
