LTC2272CUJ - 16-Bit 65Msps Serial Output ADC | Analog Devices
MPN: LTC2272CUJ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.25 | $292.50 |
| 100 | $26 | $2,600.00 |
| 500 | $23.5 | $11,750.00 |
| 1,000 | $21.25 | $21,250.00 |
LTC2272CUJ Overview
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time analog voltage or current into a discrete digital code proportional to the input magnitude. Within the broader signal-chain taxonomy, the LTC2272CUJ belongs to the high-speed pipelined ADC sub-family, which sits between successive-approximation-register (SAR) ADCs (typically <10 Msps) and flash or folding-interpolated ADCs (>250 Msps). Pipelined ADCs sample at rates from a few Msps up to several hundred Msps while delivering 12-16 bit resolution, making them the workhorse for software-defined radio, digital oscilloscopes, and base-station receivers.
Key features include an input bandwidth of 700 MHz that supports IF undersampling architectures, a PGA that lets the user optimize the full-scale range for the signal at hand, an integrated clock duty-cycle stabilizer, and differential analog inputs optimized for driving the converter with an RF transformer or differential op-amp. The serialized LVDS output conforms to the JEDEC JESD204 specification, which drastically reduces the parallel bus pin count compared with traditional CMOS or LVDS parallel ADCs.
The part is fabricated on a low-power CMOS process and includes an internal reference. Power is typically delivered from a single 1.8 V supply for the analog core and a separate 1.8 V supply for the digital LVDS output drivers, both of which can be sequenced independently to simplify power-up control.
Typical applications include cellular base-station receivers, cable CMTS upstream paths, radar digitizers, and high-end digital oscilloscopes. The wide input bandwidth also makes the LTC2272CUJ useful for IF sampling in software-defined radio (SDR) platforms and for medical ultrasound beamforming front-ends.
When designing with this converter, pay close attention to the analog input drive network - use a wideband transformer or differential amplifier and ensure the PCB layout provides controlled-impedance differential traces, a solid ground plane, and decoupling within a few millimeters of every supply pin to achieve the rated SNR and SFDR.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes that are not collected in the manufacturer datasheet.
Drop-in alternatives for LTC2272CUJ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2272CUJ (same form factor and footprint) — differing in Input Type, Output Interface, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2272CUJ#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2272CUJ#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2272IUJ
✅ Drop-In✓ In Stock
$22.1 / Unit
View Datasheet →LTC2273CUJ
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2272CUJ Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Sample Rate | 65 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth | 700 MHz |
| Output Interface | JESD204 serial (LVDS) |
| Input Type | Differential, with PGA front end |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Package | 40-pin QFN (6x6 mm), HVQCCN |
| Mounting Type | Surface Mount |
| Internal Reference | Yes |
| Clock Duty-Cycle Stabilizer | Yes |
| RoHS Status | Compliant (#PBF suffix) |
| Lead-Free | Yes (#PBF suffix) |
LTC2272CUJ Pin Configuration
| Pin 1 | AIN+ — Differential analog input positive |
| Pin 2 | AIN- — Differential analog input negative |
| Pin 3 | GND — Analog ground (per datasheet pinout) |
| Pin 4 | AVDD — 1.8 V analog supply |
| Pin 5 | AVDD — 1.8 V analog supply |
| Pin 6 | GND — Analog ground (per datasheet pinout) |
| Pin 7 | VREF — Internal reference bypass |
| Pin 8 | SENSE — Reference programming pin (per datasheet) |
| Pin 9 | REFT — Reference top bypass |
| Pin 10 | REFB — Reference bottom bypass |
| Pin 11 | GND — Analog ground (per datasheet pinout) |
| Pin 12 | AVDD — 1.8 V analog supply |
| Pin 13 | GND — Analog ground (per datasheet pinout) |
| Pin 14 | CLK+ — Differential clock input positive |
| Pin 15 | CLK- — Differential clock input negative |
| Pin 16 | AVDD — 1.8 V analog supply |
| Pin 17 | GND — Analog ground (per datasheet pinout) |
| Pin 18 | OVDD — 1.8 V output supply (LVDS) |
| Pin 19 | OGND — Output ground |
| Pin 20 | MODE — Configuration / mode select |
| Pin 21 | CS — Chip-select / configuration pin (per datasheet) |
| Pin 22 | SCK — Serial configuration clock |
| Pin 23 | SDI — Serial configuration data input |
| Pin 24 | SDO — Serial configuration data output |
| Pin 25 | OVDD — 1.8 V output supply (LVDS) |
| Pin 26 | OGND — Output ground |
| Pin 27 | OR+ — LVDS serial data output positive |
| Pin 28 | OR- — LVDS serial data output negative |
| Pin 29 | OCLK+ — LVDS serial output clock positive |
| Pin 30 | OCLK- — LVDS serial output clock negative |
| Pin 31 | OVDD — 1.8 V output supply (LVDS) |
| Pin 32 | OGND — Output ground |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | GND — Analog ground (per datasheet pinout) |
| Pin 36 | AVDD — 1.8 V analog supply |
| Pin 37 | GND — Analog ground (per datasheet pinout) |
| Pin 38 | AVDD — 1.8 V analog supply |
| Pin 39 | GND — Analog ground (per datasheet pinout) |
| Pin 40 | EP — Exposed pad - thermal/ground (must be soldered to PCB ground plane) |
Typical Applications
LTC2272CUJ is suitable for 7 applications: Cellular Base-Station Receiver IF Digitization, Software-Defined Radio (SDR) Front-End, Medical Ultrasound Beamforming, Radar and Lidar Digitization, Digital Oscilloscope and Instrumentation Front-End, Cable CMTS / Broadband Upstream Receiver, Industrial Test & Measurement Data Acquisition.
Cellular Base-Station Receiver IF Digitization
The LTC2272CUJ's 700 MHz input bandwidth and 65 Msps sample rate support IF undersampling of multi-carrier cellular signals at intermediate frequencies up to ~140 MHz. Placing the ADC downstream of a SAW filter and a low-noise IF amplifier, designers can digitize 20 MHz LTE channels directly with the on-chip PGA setting the full-scale range for optimum SNR. The JESD204 serial LVDS output routes the 16-bit data over a single differential pair to an FPGA or DSP, dramatically simplifying PCB routing versus parallel-output ADCs.
Recommended
Software-Defined Radio (SDR) Front-End
In SDR platforms the LTC2272CUJ digitizes wideband RF signals after a mixer stage, allowing software to perform channelization, demodulation, and filtering. The 700 MHz analog input bandwidth supports direct IF sampling, while the 16-bit resolution preserves dynamic range for weak-signal detection. The serial JESD204 output interfaces directly to modern FPGAs (e.g. Xilinx 7-series, Intel Cyclone V) that include JESD204 IP cores, eliminating the 16-bit parallel bus and shrinking the PCB area.
Recommended
Medical Ultrasound Beamforming
The LTC2272CUJ's single-channel 16-bit 65 Msps performance suits low-channel-count ultrasound receive paths where each channel is independently digitized before beamforming. The 700 MHz input bandwidth captures the harmonic content of returning echoes, and the differential PGA front-end optimizes the dynamic range for low-level signals from the transducer preamplifier. The JESD204 serial interface minimizes the routing congestion that plagues multi-channel ultrasound boards, simplifying thermal management and board layout.
Recommended
Radar and Lidar Digitization
Wideband radar and lidar receivers require sampling of short, high-bandwidth pulses where every dB of SNR matters. The LTC2272CUJ's 700 MHz input bandwidth and 16-bit resolution capture the full pulse shape, while the 65 Msps sample rate provides ample oversampling for matched-filter processing in an FPGA. The JESD204 output streams the digital pulse data with deterministic latency, critical for range-Doppler processing and coherent pulse accumulation.
Recommended
Digital Oscilloscope and Instrumentation Front-End
In a digital oscilloscope or spectrum-analyzer front-end, the LTC2272CUJ digitizes the conditioned signal at the input channel after the attenuator and front-end amplifier. The 700 MHz bandwidth matches the needs of a 100 MHz-class scope, while the 65 Msps rate (combined with downstream DSP interpolation) yields effective-time sampling beyond the basic Nyquist limit. The 1.8 V supply simplifies the power tree, and the small 6x6 mm QFN footprint keeps the analog front-end area compact for multi-channel layouts.
Recommended
Cable CMTS / Broadband Upstream Receiver
The LTC2272CUJ is well suited to cable-modem termination-system (CMTS) upstream paths that aggregate multiple DOCSIS channels. With 65 Msps sampling and the JESD204 interface, the ADC can feed a multi-channel DOCSIS 3.0/3.1 receiver block inside an FPGA or ASIC. The on-chip PGA front-end accommodates the wide range of upstream modulation schemes and signal levels seen in a typical head-end, and the wide input bandwidth permits direct IF digitization after the upstream diplex filter.
Recommended
Industrial Test & Measurement Data Acquisition
High-resolution industrial data-acquisition systems use the LTC2272CUJ to digitize signals from sensors such as strain gauges, LVDTs, and accelerometer outputs after analog signal conditioning. The 16-bit resolution preserves calibration accuracy, while the 700 MHz input bandwidth captures transient events such as shock or vibration bursts. The JESD204 serial output lets the data ride on a small number of differential traces back to a processor or FPGA, simplifying the wiring harness in distributed test systems.
Recommended
Recommended Products Summary
Engineering reference data for LTC2272CUJ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2272CUJ#PBF | LTC2272CUJ#TRPBF | LTC2272IUJ | LTC2273CUJ |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-40 (6x6 mm) | QFN-40 (6x6 mm) - same | QFN-40 (6x6 mm) - same | QFN-40 (6x6 mm) - same | QFN-40 (6x6 mm) - same |
| Sample Rate | 65 Msps | 65 Msps | 65 Msps | 65 Msps | 80 Msps |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Input Bandwidth | 700 MHz | 700 MHz | 700 MHz | 700 MHz | 700 MHz |
| Output Interface | JESD204 LVDS | JESD204 LVDS | JESD204 LVDS | JESD204 LVDS | JESD204 LVDS |
| Operating Temperature Range | 0 to +70 °C (commercial, C suffix) | 0 to +70 °C | 0 to +70 °C | -40 to +85 °C | 0 to +70 °C |
| Lead-Free / RoHS | Yes (#PBF RoHS-compliant) | Yes (#PBF) | Yes (#TRPBF) | Yes | Yes |
Key Differentiators
- JESD204 serial output slashes PCB routing versus parallel-output ADCs (vs LTC2217 (parallel-output 105 Msps ADC))
- Wide 700 MHz input bandwidth supports direct IF sampling (vs LTC2208 (130 Msps 16-bit parallel ADC))
- On-chip PGA front end lets the user trade full-scale range for SNR (vs LTC2257CUJ-12 (12-bit 65 Msps ADC in same QFN-40))
Design Notes
Use controlled-impedance differential traces (typically 100 Ω) for the analog inputs (AIN+/AIN-) and the clock (CLK+/CLK-); keep traces matched in length to within 0.5 mm and route them over a continuous ground plane. Place the input RC network as close as possible to the ADC pins to preserve the 700 MHz input bandwidth and avoid spurious tones. Decouple every AVDD and OVDD pin with a 0.1 µF ceramic plus a 10 µF bulk capacitor, and solder the exposed pad (pin 40) to a continuous ground copper pour for thermal dissipation and ground return.
Do not leave the MODE / configuration pins floating - tie them to AVDD or GND through resistors as described in the datasheet, otherwise the part may power up in an undefined state and the serial interface will not link. Route the LVDS serial output pairs (OR+/OR-, OCLK+/OCLK-) with 100 Ω differential impedance and a length match within 0.13 mm to satisfy JESD204 setup/hold; mismatched lengths cause data corruption on the FPGA receiver. Avoid sharing the 1.8 V analog and digital rails upstream - keep AVDD and OVDD isolated at the regulator and joined only at a single ground point to break ground loops.
Source the 65 Msps encode clock from a low-jitter clock generator such as the AD9523 or AD9517 with a phase-noise floor better than -150 dBc/Hz at 100 kHz offset; poor clock jitter directly degrades SNR according to SNR = 20·log10(1/(2π·fin·tjitter)). Keep the clock trace short and isolated from noisy digital lines; insert a transformer or differential clock buffer if the FPGA/CPU clock signal cannot meet the jitter budget. The on-chip duty-cycle stabilizer relaxes the 50 % clock duty-cycle requirement to ±5 % but does not compensate for jitter.
The QFN-40 package dissipates roughly 200 mW typical from the 1.8 V supplies; the exposed pad provides the primary heat path, so solder it to a copper pour of at least 1 sq inch connected to ground. In enclosed industrial enclosures with no airflow, drop the sample rate or ambient temperature by 5-10 °C to maintain the junction inside the 125 °C limit.
Compliance Information
RoHS-compliant and lead-free per the #PBF / #TRPBF suffix. REACH, halogen-free status, and conflict-minerals statement not confirmed in the provided data and marked 'unknown'.
