LTC2298IUP - Dual 14-Bit 65Msps 3V ADC | Analog Devices
MPN: LTC2298IUP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $62.77 | $62.77 |
| 10 | $55.5 | $555.00 |
| 100 | $39.25 | $3,925.00 |
| 500 | $28.1 | $14,050.00 |
| 1,000 | $22.4 | $22,400.00 |
LTC2298IUP Overview
A pipelined ADC is a multi-stage converter architecture that resolves an input sample in successive low-resolution sub-conversions, then digitally combines the partial results into the final high-resolution output word. This topology achieves a favorable trade-off between sample rate, resolution, and power, and it sits inside the broader analog-to-digital converter family, which in turn belongs to the data-converter category of mixed-signal integrated circuits. Pipelined ADCs dominate the >10 Msps, >10-bit performance tier, where successive-approximation (SAR) and delta-sigma ADCs cannot deliver the required throughput.
Key features include fully differential input capability, an internal sample-and-hold, programmable input range, and a CMOS-compatible parallel data interface. The device operates from a single 3V analog supply (2.7V-3.4V range) with separate analog and digital supply pins that isolate the noise-sensitive front-end from the switching outputs. Low power consumption makes the LTC2298IUP well-suited to multi-channel systems where thermal density is a concern.
Typical applications include medical imaging front-ends, multi-antenna software-defined radio (SDR) receivers, ultrasound beamforming, handheld test instrumentation, and industrial digitizers. The dual-channel integration lets system designers replace two discrete ADCs with one IC, shrinking PCB area and reducing bill-of-materials cost. Pipeline latency must be accounted for in closed-loop control applications; the LTC2298IUP is therefore preferred for open-loop data acquisition paths rather than tight servo loops.
When designing with this part, provide a clean analog ground plane, place the decoupling capacitors as close as possible to the analog (AVDD) and digital (OVDD) supply pins, and expose the EP thermal pad with multiple thermal vias to the inner ground plane. The CMOS outputs generate fast edges that should be length-matched and series-terminated to limit reflections on the parallel data bus. As of 2026-10-13, the part remains in production, so lead time should be confirmed against current distributor stock.
Drop-in alternatives for LTC2298IUP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2298IUP (same form factor and footprint) — differing in Input Type, Number of Channels, Package, RoHS Status, Sample Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2298IUP#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2298IUP#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2298CUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2297IUP
✅ Drop-In✓ In Stock
$27.75 / Unit
View Datasheet →LTC2296IUP
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2298IUP Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Analog Supply Voltage | 2.7 V to 3.4 V (single 3V supply typ.) |
| Digital I/O Supply Voltage | 2.7 V to 3.4 V |
| SNR (Nyquist input) | 74.3 dB |
| SFDR (Nyquist input) | 90 dB |
| Input Type | Differential (single-ended compatible) |
| Input Bandwidth | Up to 70 MHz and beyond |
| Data Interface | Parallel CMOS |
| Operating Temperature | -40 C to +85 C (industrial grade) |
| Package | 64-pin QFN-EP, 9x9 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix) |
| Reference Type | External or Internal (part-number dependent) |
LTC2298IUP Pin Configuration
| Pin 1 | AINA+ — Channel A positive analog input |
| Pin 2 | AINA- — Channel A negative analog input (complement) |
| Pin 3 | SENSEA — Channel A input common-mode sense / reference |
| Pin 4 | VCM — Common-mode voltage output for input bias |
| Pin 5 | REFP — Positive reference voltage decoupling |
| Pin 6 | REFN — Negative reference voltage decoupling |
| Pin 7 | VREF — Internal reference voltage bypass |
| Pin 8 | GND — Analog ground |
| Pin 9 | AINB- — Channel B negative analog input |
| Pin 10 | AINB+ — Channel B positive analog input |
| Pin 11 | SENSEB — Channel B input common-mode sense |
| Pin 12 | AVDD — Analog 3V supply (2.7-3.4 V) |
| Pin 13 | OVDD — Digital 3V I/O supply (2.7-3.4 V) |
| Pin 14 | GND — Digital ground |
| Pin 15 | CLK — Sampling clock input |
| Pin 16 | CLKOUT — Clock output (when configured as clock fan-out) |
| Pin 17 | D0A — Channel A data bit 0 (LSB) |
| Pin 18 | D1A — Channel A data bit 1 |
| Pin 19 | D2A — Channel A data bit 2 |
| Pin 20 | D3A — Channel A data bit 3 |
| Pin 21 | D4A — Channel A data bit 4 |
| Pin 22 | D5A — Channel A data bit 5 |
| Pin 23 | D6A — Channel A data bit 6 |
| Pin 24 | D7A — Channel A data bit 7 |
| Pin 25 | D8A — Channel A data bit 8 |
| Pin 26 | D9A — Channel A data bit 9 |
| Pin 27 | D10A — Channel A data bit 10 |
| Pin 28 | D11A — Channel A data bit 11 |
| Pin 29 | D12A — Channel A data bit 12 |
| Pin 30 | D13A — Channel A data bit 13 (MSB) |
| Pin 31 | OGND — Digital output ground |
| Pin 32 | OVDD — Digital 3V I/O supply |
| Pin 33 | OA0 — Channel A out-of-range indicator |
| Pin 34 | D0B — Channel B data bit 0 (LSB) |
| Pin 35 | D1B — Channel B data bit 1 |
| Pin 36 | D2B — Channel B data bit 2 |
| Pin 37 | D3B — Channel B data bit 3 |
| Pin 38 | D4B — Channel B data bit 4 |
| Pin 39 | D5B — Channel B data bit 5 |
| Pin 40 | D6B — Channel B data bit 6 |
| Pin 41 | D7B — Channel B data bit 7 |
| Pin 42 | D8B — Channel B data bit 8 |
| Pin 43 | D9B — Channel B data bit 9 |
| Pin 44 | D10B — Channel B data bit 10 |
| Pin 45 | D11B — Channel B data bit 11 |
| Pin 46 | D12B — Channel B data bit 12 |
| Pin 47 | D13B — Channel B data bit 13 (MSB) |
| Pin 48 | OB0 — Channel B out-of-range indicator |
| Pin 49 | MODE — Digital interface mode select |
| Pin 50 | CS_N — Chip select (active low) |
| Pin 51 | WR_N — Write input (active low, output latch) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | GND — Digital ground |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | GND — Analog ground |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | AVDD — Analog 3V supply |
| Pin 62 | REFLT_A — Channel A reference low-decoupling |
| Pin 63 | REFHT_A — Channel A reference high-decoupling |
| Pin 64 | EP — Exposed pad - solder to analog ground (thermal/ground) |
Typical Applications
LTC2298IUP is suitable for 6 applications: Medical Ultrasound Imaging Front-End, Multi-Antenna Software-Defined Radio (SDR), Portable Test and Measurement Instrumentation, Industrial Multi-Channel Data Acquisition, Defense and Communications IF Sampling, Image Scanner and Multi-Spectral Imaging.
Medical Ultrasound Imaging Front-End
The LTC2298IUP's dual-channel 65 Msps throughput fits naturally into multi-element ultrasound beamformer arrays where each transducer element or group of elements needs its own simultaneous A/D sampling path. With 74.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, the LTC2298IUP preserves dynamic range across the full ultrasound bandwidth (typically 2-15 MHz after downconversion), while its low power dissipation helps manage thermal density in dense 32- to 128-channel array heads. The pipelined architecture's fixed sample-clock latency is constant and channel-matched, which simplifies beam-delay calibration across the array. Place the LTC2298IUP close to the LNA outputs, route the analog inputs as length-matched 50-ohm differential pairs, and feed the parallel CMOS outputs into an FPGA back-end for channel summation and beam steering.
Recommended
Multi-Antenna Software-Defined Radio (SDR)
Software-defined radio receivers with multiple antenna inputs (e.g., MIMO or phased-array front-ends) require simultaneous sampling of two or more IF or baseband channels to preserve phase coherence for digital beamforming. The LTC2298IUP provides two simultaneously-sampling 14-bit ADCs that digitize IF signals up to 70 MHz bandwidth at 65 Msps, which covers narrowband amateur, public-safety, and cellular downlink bands with a single pair of channels. Its parallel CMOS digital interface streams samples directly into FPGAs such as Xilinx Spartan-6 or Altera Cyclone IV at full throughput without buffering. Pin-compatible dual-ADCs can be stacked to expand channel count per PCB. Use OVDD separate from AVDD to keep the digital switching noise out of the analog front-end.
Recommended
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and digital multimeters benefit from the LTC2298IUP's 65 Msps dual-channel digitization, 3V single-supply operation, and CMOS parallel output that integrates easily with low-cost microcontrollers or low-end FPGAs. The 74.3 dB SNR lets the instrument achieve better than 12 effective bits at low input frequencies, supporting the typical 0.1%-class accuracy targets of mid-range bench equipment. The exposed pad QFN-EP package keeps the PCB footprint compact, which matters when the instrument front-end area is shared with display, keypad, and battery management. Decouple AVDD and OVDD separately, route the analog ground plane unbroken under the converter, and expose the EP to a 4x4 via array for thermal sinking under continuous acquisition.
Recommended
Industrial Multi-Channel Data Acquisition
Multi-channel process-control and vibration-acquisition systems digitize simultaneous sensor signals for FFT analysis, modal testing, and condition monitoring. The LTC2298IUP can be paired in parallel with itself to expand channel count, with each dual-ADC handling two strain-gauge, accelerometer, or load-cell outputs from a multiplexer front-end. Its 14-bit resolution is sufficient for dynamic-range measurements above the sensor noise floor, while the 65 Msps rate leaves plenty of headroom for anti-aliasing filter roll-off. Industrial-grade -40 C to +85 C operation allows deployment in factory-floor and outdoor cabinets. Place a per-channel input buffer (e.g., AD8021) to drive the ADC differential inputs, and use a common clock fanout buffer such as LTC6957 to guarantee tight channel-to-channel phase alignment.
Recommended
Defense and Communications IF Sampling
IF sampling receivers in electronic-warfare and microwave-link systems digitize intermediate-frequency signals in the 10-70 MHz range directly into the digital domain. The LTC2298IUP's 90 dB SFDR provides strong tolerance to large out-of-band blockers, while 74.3 dB SNR maintains sensitivity to small in-band targets. The dual-channel integration lets the same IC digitize two IF outputs from I/Q demodulation, enabling single-IC digital I/Q processing for the receiver. Wideband inputs support flexible tuning plans, and the 3V single supply simplifies power tree design in size-, weight-, and power-constrained (SWaP) platforms. Use trace-impedance-matched 100-ohm differential pairs on the analog side and source-series-terminated clock distribution to keep sampling jitter below 1 ps for full-SFDR preservation.
Recommended
Image Scanner and Multi-Spectral Imaging
Line-scan cameras and multi-spectral imaging systems digitize pixel streams from linear photodiode arrays or color-filtered sensors. The LTC2298IUP's dual-channel simultaneous sampling allows capture of two sensor arrays (e.g., visible and near-infrared) per chip, halving the ADC count and saving board area. With 65 Msps and 14-bit resolution, the IC keeps pace with high-speed linescan cameras running at 100+ kHz line rates, while 3V single-supply operation eases battery or USB-powered imaging designs. The parallel CMOS output streams pixel data into an FPGA or ASIC for line buffering and image reconstruction. Provide a low-noise transimpedance amplifier front-end (e.g., AD8015) to drive the ADC differential inputs, and ground the EP firmly through a thermal-via array.
Recommended
Recommended Products Summary
Engineering reference data for LTC2298IUP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2298IUP#PBF | LTC2298IUP#TRPBF | LTC2298CUP | LTC2297IUP | LTC2296IUP |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-pin QFN-EP (9x9 mm) | 64-pin QFN-EP (9x9 mm) - same | 64-pin QFN-EP (9x9 mm) - same | 64-pin QFN-EP (9x9 mm) - same | 64-pin QFN-EP (9x9 mm) - same | 64-pin QFN-EP (9x9 mm) - same |
| Sample Rate (per channel) | 65 Msps | 65 Msps | 65 Msps | 65 Msps | 40 Msps (-38%) | 25 Msps (-62%) |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| SNR (Nyquist) | 74.3 dB | 74.3 dB | 74.3 dB | 74.3 dB | 74.3 dB | 74.3 dB |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| Supply Voltage | 3 V (2.7-3.4 V) | 3 V (2.7-3.4 V) | 3 V (2.7-3.4 V) | 3 V (2.7-3.4 V) | 3 V (2.7-3.4 V) | 3 V (2.7-3.4 V) |
| Packaging / Finish | Tube (SnPb possible) | Tube - lead-free / RoHS | Tape & Reel - lead-free / RoHS | Tube - commercial grade | Tube - industrial grade | Tube - industrial grade |
Key Differentiators
- Dual simultaneously-sampling ADCs in one package (vs LTC2206IUK / alternative single-channel 65 Msps ADC)
- Wide-bandwidth analog inputs usable for IF sampling (vs LTC2206IUK / generic 65 Msps ADC with limited input bandwidth)
- Industrial temperature grade vs. commercial-only drop (vs LTC2298CUP (commercial-only, 0 to +70 C variant))
- Drop-in 40 Msps option in same package (vs LTC2297IUP (pin-compatible lower-speed variant))
Design Notes
Use a continuous, unbroken analog ground plane on the top layer directly under the LTC2298IUP, with the EP (exposed pad) thermally and electrically bonded to this plane via a 4x4 to 6x6 grid of thermal vias (0.3-0.5 mm drilled, plated, and capped). Route analog input traces as 100-ohm differential pairs, length-matched within 1 mm between the two halves of each pair. Avoid routing digital outputs across the analog input region on inner layers, and keep the parallel CMOS bus on the opposite side of the PCB from the analog front-end. Place 10 uF + 0.1 uF decoupling caps directly on the AVDD and OVDD pin pairs, with short, wide traces to the supply and ground vias. (Estimated: thermal-via array count based on Analog Devices EP-pad thermal-design guidance; verify against the specific PCB stackup in the manufacturer's datasheet application notes.)
The LTC2298IUP's parallel CMOS outputs toggle simultaneously, creating large edge-rate (di/dt) currents on the OVDD/OGND power pins. Place the output data lines as short microstrips terminated with a series resistor (typically 22-33 ohm) at the FPGA side to absorb reflections and limit ringing. Route the clock signal in a controlled-impedance trace and use a low-jitter clock fan-out buffer (e.g., LTC6957) for multi-channel synchronization - jitter above 1 ps RMS degrades SNR toward the Nyquist limit and reduces SFDR. Add 22-33 ohm series damping on the CLK line near the ADC clock input to prevent clock-line reflections from re-entering the analog front-end.
Do not exceed the absolute maximum OVDD voltage of 3.6 V (the part is not 5 V tolerant). Ensure the pipelined latency (typically 5 clock cycles plus delay) is accounted for in any closed-loop control application - the LTC2298IUP is not appropriate for tight servo loops. Avoid using the same clock for sampling and FPGA output capture if the FPGA has a long output path; instead, supply the ADC clock from a low-jitter dedicated clock generator, and align the FPGA capture edge to the ADC's CLKOUT when the device is configured for output clocking. Finally, make sure the analog input common-mode voltage is in the range required by the part; violation will degrade SNR significantly. (Estimated: pipelined latency value of '5 cycles' is a typical pipelined-ADC figure; confirm exact pipeline depth against the LTC2298IUP datasheet timing diagrams.)
Group all analog-related components on the analog side and digital components on the digital side of the LTC2298IUP; do not place the input sampling capacitors or reference decoupling caps on the wrong side of the package. Pair each supply pin with its corresponding ground pin, and do not allow signal lines to pass between supply and ground vias - route them around the power-pin pairs. When stacking multiple LTC2298IUPs for higher channel count, mirror the layout across the chip, and keep at least 5 mm between adjacent exposed pads to maintain unimpeded thermal venting on a 4-layer 1 oz copper PCB.
Compliance Information
RoHS/lead-free compliance applies to the #PBF and #TRPBF shipping suffixes. Non-PBF (SnPb) versions exist for legacy aerospace/defense use. AEC-Q100 qualification is not specified by the manufacturer for this part family.
