LTC2341HUH-16 - Dual 16-Bit 666ksps SAR ADC | Analog Devices
MPN: LTC2341HUH-16 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $30.2 | $302.00 |
| 100 | $26.85 | $2,685.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $21.75 | $21,750.00 |
LTC2341HUH-16 Overview
A SAR ADC is a type of analog-to-digital converter that uses a successive approximation register and an internal DAC to converge on the input voltage one bit per clock cycle. Compared to delta-sigma ADCs, SAR converters deliver deterministic latency, single-cycle conversions, and excellent DC accuracy, making them well suited to multiplexed data-acquisition systems, control loops, and instrumentation. The dual simultaneous-sampling architecture lets the LTC2341HUH-16 capture two channels with channel-to-channel skew of only a few nanoseconds.
Key features include 16-bit resolution with no missing codes, 86.5 dB SNR (typical at ±4.096V range), pin-selectable SPI CMOS or LVDS interfaces, an internal 4.096V reference with integrated buffer, and per-channel soft-span input ranges. The device supports an external reference option for designs that need ratiometric measurements or non-standard full scales.
Technically, the SAR core is built on a switched-capacitor charge-redistribution architecture with an integrated front-end multiplexer; the analog inputs are truly differential and the wide common-mode range allows direct connection to bipolar signals, single-ended rails, and ground-referenced transducers without external level shifting. Built-in reference decoupling and an internal buffer minimize external component count and reduce PCB footprint.
Typical applications include multichannel data-acquisition systems, industrial process control, instrumentation, automatic test equipment (ATE), and any design that requires simultaneous sampling of two analog signals with deterministic latency. The part is also a strong fit for multi-axis motor control and vibration analysis, where phase coherence between channels is critical.
When designing with the LTC2341HUH-16, ensure clean analog and digital ground separation and place the 10uF reference bypass capacitor as close to the REFIN pin as possible. Use controlled-impedance routing for LVDS lines when the LVDS interface is selected at high throughput, and verify the digital I/O logic-level compatibility (CMOS mode supports 1.8V to 5V VIO).
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, with all specifications cross-referenced against the Analog Devices LTC2341-16 datasheet (234116f).
Drop-in alternatives for LTC2341HUH-16 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2341HUH-16 (same form factor and footprint) — differing in Package, Resolution, Sample Rate, RoHS Status, Analog Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2341HUH-18
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$24.95 / Unit
View Datasheet →LTC2340HUH-16
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2249IUH
✅ Drop-In✓ In Stock
$20.85 / Unit
View Datasheet →LTC2245IUH
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →LTC2237IUH
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →LTC2241IUP-12
✅ Drop-In✓ In Stock
$34.5 / Unit
View Datasheet →LTC2341HUH-16 Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | SAR (Successive Approximation Register) |
| Sample Rate | 666 ksps per channel |
| Input Type | Differential, wide common-mode range |
| Input Ranges (SoftSpan) | ±4.096 V, 0 to 4.096 V, ±2.048 V, 0 to 4.096 V |
| Supply Voltage | 5 V |
| Reference | Internal 4.096 V with buffer (external reference option) |
| Digital Interface | Pin-selectable SPI CMOS (1.8 V to 5 V) or LVDS |
| CMOS Output Lanes | 1 or 2 lanes (selectable) |
| Package | 32-QFN (5x5 mm), UH suffix |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead Free | Yes (PBF suffix) |
LTC2341HUH-16 Pin Configuration
| Pin 1 | REFCAP — Internal reference bypass (10 µF ceramic to GND) |
| Pin 2 | VIO — Digital I/O supply (1.8 V to 5 V) |
| Pin 3 | DGND — Digital ground |
| Pin 4 | VLX1+ — LVDS channel-1 positive output (LVDS mode) / OUT1 (CMOS mode) |
| Pin 5 | VLX1- — LVDS channel-1 negative output (LVDS mode) / DNC (CMOS mode) |
| Pin 6 | VLX2+ — LVDS channel-2 positive output (LVDS mode) / OUT2 (CMOS mode) |
| Pin 7 | VLX2- — LVDS channel-2 negative output (LVDS mode) / DNC (CMOS mode) |
| Pin 8 | AGND — Analog ground |
| Pin 9 | AIN1+ — Channel-1 positive analog input |
| Pin 10 | AIN1- — Channel-1 negative analog input |
| Pin 11 | AIN2+ — Channel-2 positive analog input |
| Pin 12 | AIN2- — Channel-2 negative analog input |
| Pin 13 | VREF — Internal 4.096 V reference output / external reference input |
| Pin 14 | REFLO — Reference ground return |
| Pin 15 | OGND — LVDS/output ground reference |
| Pin 16 | OVR — Over-range indicator (open-drain, active low) |
| Pin 17 | SDOUT — Serial data output (CMOS mode) |
| Pin 18 | SCK — Serial clock input |
| Pin 19 | CNV — Convert / start-of-conversion input |
| Pin 20 | BUSY — Conversion busy output (active high) |
| Pin 21 | SDI — Serial data input (programming SoftSpan range and read-back) |
| Pin 22 | LVDC — Logic-level/CMOS-LVDS mode select (high = LVDS, low = CMOS) |
| Pin 23 | RDL — Read strobe, output channel-1 select (CMOS mode) |
| Pin 24 | RDLA — Read strobe A, alternates with RDL (CMOS dual-lane mode) |
| Pin 25 | VDD — Analog 5 V supply |
| Pin 26 | AGND — Analog ground |
| Pin 27 | AGND — Analog ground |
| Pin 28 | AGND — Analog ground |
| Pin 29 | AGND — Analog ground |
| Pin 30 | AGND — Analog ground |
| Pin 31 | AGND — Analog ground |
| Pin 32 | EP — Exposed pad - tie to AGND on PCB for thermal dissipation |
Typical Applications
LTC2341HUH-16 is suitable for 7 applications: Multichannel Data Acquisition System, Industrial Process Control and Instrumentation, Automatic Test Equipment (ATE) and Bench Instruments, Motor Control and Drive Monitoring, Vibration and Acoustic Analysis, Medical Monitoring Equipment, Power Quality and Energy Meters.
Multichannel Data Acquisition System
The LTC2341HUH-16's dual simultaneous-sampling 16-bit SAR channels at 666 ksps each make it a natural fit for multi-channel data-acquisition front ends. With 86.5 dB SNR in the ±4.096 V range and a wide common-mode input, two sensors can be digitized per IC without inter-channel skew, reducing board area relative to two separate ADC channels. The internal 4.096 V reference and buffer eliminate the need for an external reference IC, simplifying the BOM. A typical circuit uses 0.1 µF + 10 µF decoupling on the 5 V analog rail, a ferrite bead to the digital rail, and three CS5530-style op-amp drivers per channel to preserve the datasheet SNR.
Recommended
Industrial Process Control and Instrumentation
In PLCs, thermocouple and strain-gauge signal-conditioning front ends, the LTC2341HUH-16's differential ±4.096 V input range accepts bipolar transducer outputs directly with no level shifting. The 666 ksps per channel throughput exceeds most industrial control loops (1 kHz typical), giving headroom for diagnostic sampling. The pin-selectable SPI CMOS or LVDS interface lets the same part serve a 1.8 V MCU-based remote I/O or a 3.3 V Cortex-M4 host. Built-in per-channel range switching means one channel can digitize a 4-20 mA loop (scaled) while the other reads a 0-10 V actuator signal.
Recommended
Automatic Test Equipment (ATE) and Bench Instruments
ATE source-measurement units and bench multimeters need 16-bit resolution with low inter-channel skew so that two measurements can be compared at the same instant - exactly what the LTC2341HUH-16 delivers. The soft-span configurability means a single ATE pin card can digitize ±4.096 V and 0-4.096 V DUT signals without changing the ADC. The LVDS interface option simplifies routing across the backplane to a controller FPGA, minimizing EMI in a dense tester. Combined with the LTC6237 driver, the part achieves >82 dB SINAD as documented in the LTC2341-16 datasheet.
Recommended
Motor Control and Drive Monitoring
Three-phase motor controllers use the LTC2341HUH-16 to digitize current and voltage feedback simultaneously on each phase. With two channels, designers can capture phase-A current and phase-B current with picosecond skew, enabling clean d-q transformations and high-bandwidth torque control. The 666 ksps per channel throughput is sufficient for 50 kHz FOC loops at 1000 samples per electrical cycle. The differential inputs reject 24 V bus common-mode transients, while the 5 V supply integrates cleanly into the motor-drive power tree.
Recommended
Vibration and Acoustic Analysis
FFT-based vibration analysis requires phase-coherent sampling across multiple accelerometers to compute modal-shape and cross-spectra. The LTC2341HUH-16's simultaneous-sampling architecture eliminates the ratiometric error common when multiple channels are sequenced, and 16-bit dynamic range captures more than 90 dB of the accelerometer signal. The 666 ksps per channel rate supports bandwidths well above the 20 kHz audio band. The wide-band noise floor (~100 dBFS) documented in the LTC2341-16 datasheet keeps spurious components below the noise floor of MEMS-class accelerometers.
Recommended
Medical Monitoring Equipment
Patient-monitoring systems and ECG front ends benefit from the LTC2341HUH-16's low-noise 16-bit sampling and simultaneous-sampling channels. Two channels can capture lead-I and lead-II ECG traces with synchronized sampling, enabling real-time vectorcardiography without post-processing artifact. The wide common-mode input directly accepts bipolar electrode signals after front-end amplification, while the 5 V supply isolates cleanly from the 24 V medical-rail domain. The internal reference tightens absolute voltage accuracy for calibration.
Recommended
Power Quality and Energy Meters
Multi-phase energy meters and power-quality analyzers use the LTC2341HUH-16 to digitize voltage and current channels per phase. The simultaneous sampling allows accurate active/reactive power calculation without phase-skew error, while the 16-bit dynamic range supports IEC 62053-22 class-0.2 / 0.5 meter accuracy classes in favorable topologies. The pin-selectable 1.8 V to 5 V VIO interface allows direct connection to processors like the MAX32652 or ADI MAX78002, removing level shifters and reducing BOM cost.
Recommended
Recommended Products Summary
Engineering reference data for LTC2341HUH-16 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2341HUH-18 | LTC2340HUH-16 | LTC2249IUH | LTC2245IUH | LTC2237IUH | LTC2241IUP-12 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-QFN (5x5) UH | 32-QFN (5x5) UH - same | 32-QFN (5x5) UH - same | 32-QFN (5x5) UH - same footprint family | 32-QFN (5x5) UH - same footprint family | 32-QFN (5x5) UH - same footprint family | 32-QFN (5x5) UH - same footprint family |
| Resolution | 16 bit | 18 bit | 16 bit | 14 bit | 14 bit | 10 bit | 12 bit |
| Sample Rate | 666 ksps/ch (2 ch simultaneous) | 666 ksps/ch (2 ch simultaneous) | 230 ksps (single ch) | 80 Msps (pipelined) | 10 Msps (pipelined) | 40 Msps (pipelined) | 65 Msps (pipelined) |
| Architecture | SAR | SAR | SAR | Pipelined | Pipelined | Pipelined | Pipelined |
| Channels (simultaneous) | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
| Input Type | Differential, wide common-mode range | Differential, wide common-mode range | Differential, wide common-mode range | Differential | Differential | Differential | Differential |
| Digital Interface | SPI CMOS 1.8-5V / LVDS | SPI CMOS 1.8-5V / LVDS | SPI CMOS 1.8-5V / LVDS | Parallel LVDS/PECL | Parallel LVDS | Parallel LVDS/CMOS | Parallel LVDS |
| Supply Voltage | 5 V | 5 V | 5 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
Key Differentiators
- Dual simultaneous-sampling 16-bit channels in a 5x5 mm QFN (vs LTC2340HUH-16 (single-channel 230 ksps))
- SoftSpan input ranges selectable per-conversion per-channel (vs LTC2245IUH (fixed-bipolar pipelined input stage))
- Pin-selectable SPI CMOS (1.8-5 V) or LVDS interface (vs LTC2249IUH (parallel LVDS/PECL))
- Internal 4.096 V reference with integrated buffer (vs LTC2341-16 external reference designs)
Design Notes
Separate analog and digital ground planes and join them only at the device ground pins. Route the analog inputs (AIN1+, AIN1-, AIN2+, AIN2-) as matched, length-tuned differential pairs on a stripline or microstrip stack-up with a characteristic impedance of 50 Ω (with 100 Ω termination between the pair). Place the 10 µF REFCAP bypass directly at pin 1 with the shortest possible trace. The exposed pad (pin 32) MUST be soldered to an analog ground copper pour for thermal dissipation; not soldering it can result in 30-40% higher thermal resistance.
Power VDD with 5 V from a low-noise LDO such as LT3042 or LT3045; add a pi-filter (ferrite plus 0.1 µF + 10 µF ceramics) to suppress switcher noise from upstream rails. Power VIO independently from the host MCU rail through a ferrite bead to keep digital switching noise out of the analog core. Decoupling: at minimum, 0.1 µF X7R 0402 or 0603 within 1 mm of every supply pin, with one bulk 10 µF X5R per supply rail near the device.
In LVDS mode (LVDC tied high), route the VLX1+/-, VLX2+/- outputs as 100 Ω differential pairs, kept isolated from clock and high-noise digital traces. Source-series termination is not generally needed on the LTC2341 LVDS outputs, but clean via stitching is required every 4-6 mm to the ground plane. For CMOS two-lane mode, both SDOUT edges can reach 50 MHz; treat them as transmission lines above 30 mm of trace length.
Do not exceed the CMVR of the analog inputs - measured to the AGND-VDD rail, not relative to the host logic. If the input source is DC-coupled with >12 V common-mode, add an active input attenuator and level shifter (e.g., LT1995). When switching between SoftSpan ranges during a conversion burst, ensure CNV meets the tACQ acquisition time >217 ns, otherwise channel-to-channel crosstalk can degrade SNR by 6-10 dB.
Place the ADC directly adjacent to the analog input connectors or protection circuits to minimize loop inductance and prevent RF injection. The SCK traces should be guarded by ground traces on each side to prevent coupling to analog inputs. Reference routing should be routed as a wide star from the REFCAP, avoiding any digital or power traces. Estimate: on a 4-layer FR-4 with 1 oz copper, the thermal pad area needed for 0.5 W dissipation at 85 °C ambient junction is roughly 1 cm² of unbroken copper on the top and inner planes.
Compliance Information
RoHS/lead-free per Analog Devices product page and DigiKey listing (#PBF suffix). Halogen-free not specified in the verified data - flagged as unknown. AEC-Q100 not applicable (industrial/consumer part). REACH compliance reflects datasheet conflict-mineral language; not separately stated in the verified data.
