LTC2249IUH - 14-Bit 80Msps Low Power ADC | Analog Devices
MPN: LTC2249IUH ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.25 | $292.50 |
| 100 | $26.1 | $2,610.00 |
| 500 | $23.4 | $11,700.00 |
| 1,000 | $20.85 | $20,850.00 |
LTC2249IUH Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sampling rate. ADCs sit at the boundary between the analog front-end (sensors, amplifiers, filters) and the digital back-end (FPGAs, DSPs, microcontrollers) in a signal chain, and their sampling rate, resolution, and dynamic range determine the usable bandwidth and fidelity of the entire system. The LTC2249IUH occupies the high-speed, mid-resolution tier of this taxonomy: ADC > pipelined ADC > 14-bit 80Msps ADC > power management/data conversion mixed-signal IC > semiconductor.
Key features include a flexible differential input range of 1V to 2V peak-to-peak, a 575MHz full-power analog input bandwidth, optional internal dither for improved low-amplitude linearity, and a single 3V supply (2.85V to 3.4V). Power consumption is 222mW at 80Msps, and the part offers a shutdown/nap mode that drops quiescent current to microampere levels for power-cycled applications. The 32-lead QFN package with an exposed die-attach pad provides a low thermal resistance path for the internal 222mW dissipation.
The LTC2249 uses a pipelined multi-stage switched-capacitor architecture with digital output error correction, which is the standard topology for 14-bit 80Msps converters and which allows the high sample rate without the latency of a successive-approximation register (SAR) architecture. The 14-bit parallel CMOS/TTL-compatible output bus and the on-chip sample-and-hold eliminate the need for an external track-and-hold amplifier in most applications.
Typical applications include cellular basestation receivers, medical imaging front-ends (ultrasound, digital x-ray), cable-headend DOCSIS downstream digitizers, and high-end test-and-measurement instrumentation. The combination of wide input bandwidth, dither, and high SFDR makes the part well suited to undersampling IF signals in software-defined radio (SDR) and communications receivers.
When designing with the LTC2249IUH, pay attention to the analog input network: the device expects a 50-ohm-terminated differential drive, and a transformer (e.g., ADT1-1WT) or a high-speed differential op-amp (e.g., AD8138) is typically used to convert single-ended signals to the required differential form. Use a solid ground plane under the exposed pad (EP) and stitch vias around the perimeter to manage the 222mW dissipation and to keep the digital return currents from coupling into the analog inputs.
This page synthesizes distributor pricing, drop-in same-package alternatives drawn from the LTC22xx family, and practical design notes not found in the manufacturer datasheet alone, providing a single reference for component selection, PCB layout, and signal-chain design.
Drop-in alternatives for LTC2249IUH — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2249IUH (same form factor and footprint) — differing in Package, RoHS Status, Sample Rate, Resolution, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2249IUH#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2249CUH
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2250IUH
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2248IUH
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2251IUH
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2249IUH Maximum Ratings & Electrical Characteristics
| Resolution | 14 bits |
| Sample Rate | 80 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| Supply Voltage (VDD) | 2.85 V to 3.4 V (3 V typical) |
| Power Dissipation | 222 mW at 80 Msps |
| SNR | 73 dB at 70 MHz input |
| SFDR | 90 dB at 70 MHz input |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.5 LSB |
| Full-Power Analog Input Bandwidth | 575 MHz |
| Differential Input Range | 1 V to 2 V peak-to-peak |
| Data Interface | Parallel CMOS/TTL |
| Package | 32-Pin QFN (5x5) with Exposed Pad (UH) |
| Operating Temperature Range | -40 °C to +85 °C (industrial) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (Pb-free PBF suffix) |
| Data Output Format | Offset Binary / Two's Complement (selectable) |
LTC2249IUH Pin Configuration
| Pin 1 | GND — Ground return for analog and digital sections |
| Pin 2 | AIN+ — Positive differential analog input |
| Pin 3 | AIN- — Negative differential analog input |
| Pin 4 | VREF — Voltage reference decoupling pin |
| Pin 5 | SENSE — Reference configuration (grounded for internal reference) |
| Pin 6 | VCM — Common-mode voltage output for input driver bias |
| Pin 7 | VDD — 3V analog supply |
| Pin 8 | GND — Analog ground |
| Pin 9 | OGND — Output driver ground |
| Pin 10 | OVDD — Output driver supply (set by logic level) |
| Pin 11 | D13 — Data output bit 13 (MSB) |
| Pin 12 | D12 — Data output bit 12 |
| Pin 13 | D11 — Data output bit 11 |
| Pin 14 | D10 — Data output bit 10 |
| Pin 15 | D9 — Data output bit 9 |
| Pin 16 | D8 — Data output bit 8 |
| Pin 17 | D7 — Data output bit 7 |
| Pin 18 | D6 — Data output bit 6 |
| Pin 19 | D5 — Data output bit 5 |
| Pin 20 | D4 — Data output bit 4 |
| Pin 21 | D3 — Data output bit 3 |
| Pin 22 | D2 — Data output bit 2 |
| Pin 23 | D1 — Data output bit 1 (LSB when 14-bit mode) |
| Pin 24 | D0 — Data output bit 0 |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | CLK+ — Positive differential clock input |
| Pin 27 | CLK- — Negative differential clock input |
| Pin 28 | OF — Overflow output flag |
| Pin 29 | MODE — Output mode select (offset binary or two's complement) |
| Pin 30 | DITH — Dither enable input (high enables internal dither) |
| Pin 31 | SHDN — Shutdown input (active high, nap mode when low) |
| Pin 32 | NC — Not connected (per datasheet) |
Typical Applications
LTC2249IUH is suitable for 6 applications: Cellular Basestation Receiver, Medical Imaging (Ultrasound), Cable Headend / DOCSIS Downstream, Test and Measurement Instrumentation, Software-Defined Radio (SDR) Receiver, Radar and Lidar Signal Processing.
Cellular Basestation Receiver
The LTC2249IUH is well matched to cellular basestation receiver IF digitizers because its 73 dB SNR at 70 MHz and 90 dB SFDR support demodulation of QAM and QPSK waveforms with low EVM. The 80 Msps sample rate aligns with the symbol rates used in UMTS and LTE receivers operating at 70 MHz or 140 MHz IF frequencies, allowing the part to undersample IF signals above Nyquist and fold them into baseband, eliminating one downconversion stage. The 222 mW power budget fits within the basestation's per-channel thermal envelope, and the 32-QFN package with exposed pad provides the thermal path required for continuous operation. Recommended companion parts: AD8138 differential driver, ADT1-1WT RF transformer, and a clock jitter cleaner.
Recommended
Medical Imaging (Ultrasound)
The LTC2249IUH is a strong fit for medical ultrasound beamformer front-ends that digitize the received RF echo at IF frequencies between 5 MHz and 50 MHz. The 14-bit resolution preserves the dynamic range required for speckle contrast and harmonic imaging, while the 73 dB SNR ensures that low-amplitude echoes from deep tissue are not buried in quantization noise. The 80 Msps rate supports multi-channel parallel acquisition, with each channel requiring a separate LTC2249 to maintain channel-to-channel phase coherence. The industrial -40 °C to +85 °C temperature rating supports the regulated thermal environment of cart-based and portable ultrasound systems. Recommended companion parts: AD8045 op-amp front-end, AD9516 clock generator.
Recommended
Cable Headend / DOCSIS Downstream
The LTC2249IUH suits DOCSIS 3.0/3.1 cable-headend downstream receivers that digitize a 50 MHz to 1 GHz cable spectrum. Its 575 MHz full-power input bandwidth allows direct-IF sampling of the downstream band without an external downconversion mixer, and its 90 dB SFDR at 70 MHz is sufficient to handle the high MER (modulation error ratio) demands of 256-QAM and 1024-QAM downstream channels. The single 3V supply and 222 mW dissipation fit within the rack-density thermal budget of headend chassis, and the parallel CMOS output bus is easy to interface to FPGAs from Altera or Xilinx. Recommended companion parts: AD8370 VGA, AD815 amplifier buffer.
Recommended
Test and Measurement Instrumentation
The LTC2249IUH is well suited to high-end digital oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers where 14-bit resolution at 80 Msps enables accurate capture of transient and modulated signals. The 73 dB SNR provides wide dynamic range for measuring small signal details, while the differential input and flexible 1V-2V input range simplify the front-end attenuator and clamp design. The internal optional dither improves SFDR at low input amplitudes, which is important when measuring harmonics of a low-level stimulus. The 32-QFN exposed-pad package supports bench-instrument thermal designs with a 222 mW continuous load. Recommended companion parts: AD8138 driver, ADR431 precision 2.5V reference for calibration.
Recommended
Software-Defined Radio (SDR) Receiver
The LTC2249IUH fits SDR and wideband receiver designs that use bandpass sampling to digitize IF signals above Nyquist. The 575 MHz input bandwidth allows the same ADC to be reused across HF, VHF, and low-UHF receiver chains by changing only the front-end filter, and the 90 dB SFDR at 70 MHz preserves the dynamic range needed for weak-signal detection in amateur, military, and commercial SDR platforms. The 80 Msps rate is sufficient for narrowband channel bandwidths up to 30 MHz after digital downconversion in the FPGA. The shutdown/nap mode reduces supply current between active reception windows, supporting battery-powered portable SDR. Recommended companion parts: AD9864 mixed-signal front-end, AD9516 low-jitter clock.
Recommended
Radar and Lidar Signal Processing
The LTC2249IUH is a good match for short-range radar and lidar receiver IF digitizers that require wide dynamic range at moderate sample rates. The 14-bit resolution captures both the strong return from nearby targets and the weak return from distant or stealthy targets in the same acquisition, which is critical for automotive obstacle-detection and industrial level-sensing applications. The 80 Msps rate digitizes pulsed RF envelopes up to 40 MHz, and the differential input rejects common-mode noise from the digital switching in the host DSP. The 222 mW power and the QFN-32 footprint are compatible with compact multi-channel sensor modules. Recommended companion parts: AD8021 op-amp IF amp, AD9854 frequency synthesizer.
Recommended
Recommended Products Summary
Engineering reference data for LTC2249IUH — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2249IUH#TRPBF | LTC2249CUH | LTC2250IUH | LTC2248IUH | LTC2251IUH |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-QFN (5x5) with EP | 32-QFN (5x5) with EP - same | 32-QFN (5x5) with EP - same | 32-QFN (5x5) with EP - same | 32-QFN (5x5) with EP - same | 32-QFN (5x5) with EP - same |
| Resolution | 14 bit | 14 bit - same | 14 bit - same | 10 bit - lower | 14 bit - same | 14 bit - same |
| Sample Rate | 80 Msps | 80 Msps - same | 80 Msps - same | 80 Msps - same | 65 Msps - lower (-19%) | 125 Msps - higher (+56%) |
| Power Dissipation | 222 mW at 80 Msps | 222 mW - same | 222 mW - same | 222 mW - same | 195 mW - lower | 320 mW - higher (+44%) |
| SNR at 70 MHz | 73 dB | 73 dB - same | 73 dB - same | 61.5 dB - lower | 73 dB - same | 72.7 dB - similar |
| SFDR at 70 MHz | 90 dB | 90 dB - same | 90 dB - same | 84 dB - lower | 90 dB - same | 88 dB - similar |
| Input Bandwidth | 575 MHz | 575 MHz - same | 575 MHz - same | 575 MHz - same | 575 MHz - same | 640 MHz - higher |
| Operating Temperature | -40 °C to +85 °C (industrial) | -40 °C to +85 °C - same | 0 °C to +70 °C (commercial) | -40 °C to +85 °C - same | -40 °C to +85 °C - same | -40 °C to +85 °C - same |
| Supply Voltage | 2.85 V to 3.4 V (3 V typ) | 2.85 V to 3.4 V - same | 2.85 V to 3.4 V - same | 2.85 V to 3.4 V - same | 2.85 V to 3.4 V - same | 2.85 V to 3.4 V - same |
Key Differentiators
- Industrial -40 °C to +85 °C operating temperature with 14-bit 80 Msps spec (vs LTC2249CUH)
- Higher resolution than the LTC2250 family at the same sample rate (vs LTC2250IUH)
- Lower power and smaller package than the LTC2209 family at the same 80 Msps (vs LTC2209IUP)
Design Notes
Estimated: use a 4-layer PCB with continuous ground plane under the QFN-32 exposed pad. Stitch at least 8 ground vias around the EP perimeter (0.3 mm drill, 0.6 mm pad) to provide low-inductance return for the 222 mW dissipation and to keep digital return currents from coupling into the analog inputs. Route the differential clock and analog inputs as 50-ohm controlled-impedance traces with matched length (±0.5 mm) to maintain sampling accuracy.
Drive the LTC2249IUH analog inputs differentially using a high-bandwidth op-amp such as AD8138 or a 1:1 RF transformer such as ADT1-1WT. A single-ended drive reduces SNR by 3 dB and degrades SFDR. The differential clock must come from a low-jitter source such as AD9516 or a clean sine-wave clock generator; clock jitter of 1 ps RMS degrades SNR at 70 MHz by approximately 2 dB.
Estimated: decouple each VDD pin with a 0.1 µF X7R 0402 ceramic placed within 1 mm of the pin, and place one 10 µF X5R 0805 bulk capacitor on the analog and digital supply rails. Ferrite beads (e.g., BLM18PG221SN1) between the analog and digital supplies reduce switching-noise coupling. The 222 mW continuous dissipation requires that the 32-QFN EP be soldered to a copper pour of at least 1 square inch to keep junction temperature below 100 °C.
Do not float the SENSE pin; ground it to enable the internal 1.5 V reference. Do not leave DITH floating - tie it high to enable the internal dither that improves SFDR for low-amplitude inputs below -20 dBFS. The MODE pin selects between offset-binary and two's-complement output; verify your FPGA or DSP expects the correct format before PCB layout. The shutdown pin should be pulled low in normal operation and driven high only for power-cycled designs.
Compliance Information
Pb-free per #PBF suffix. RoHS3 compliant and REACH unaffected per PartGenie AI analysis. Not AEC-Q100 qualified; the part is not marketed for automotive safety-critical applications.
