MAX109EHF-D - 8-Bit 2.2Gsps ADC with T/H and LVDS | Maxim
MPN: MAX109EHF-D ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
MAX109EHF-D Overview
A high-speed ADC is a data converter that samples an analog input at a rate equal to or greater than twice the highest input frequency component, producing a digital word whose magnitude is proportional to the instantaneous input voltage. At 2.2 Gsps the MAX109EHF-D sits in the high-speed converter tier above general-purpose ADCs (typically 1 Msps to 250 Msps) but below the highest-end oscilloscope-grade parts (>5 Gsps). It belongs to the broad hierarchy of data converters -> ADCs -> high-speed ADCs -> interleaved flash ADCs, used wherever an analog waveform must be frozen and quantized into digital words with minimal aperture delay.
Key features include the on-chip differential track-and-hold that reduces aperture uncertainty, the 1:4 LVDS output demultiplexer that lowers each output lane to 550 MHz to ease FPGA capture, and a 3.0 V to 3.6 V LVDS supply rail that interfaces directly to 3.3 V-referenced FPGAs. An analog supply of -5.2 V plus a 5 V analog rail power the input core, and the part supports interleaving of two MAX109 devices to reach 4.4 Gsps aggregate rate for two-channel direct-IF digitization.
The device uses a pipelined multi-stage flash architecture fabricated on Maxim's advanced low-voltage silicon process, achieving 48 dB SNR and 60 dB SFDR typical at 2.2 Gsps with a 500 MHz input. The integrated T/H front end has sub-picosecond aperture jitter, which preserves SNR on IF frequencies beyond 1 GHz where aperture jitter dominates total noise.
Typical applications include direct-IF digitization in software-defined radio receivers, radar I/Q baseband digitizers, digital oscilloscope front-end channels, high-speed test-and-measurement instrumentation, and broadband communications test gear. The 1:4 demuxed LVDS output is also well matched to FPGA LVDS receivers in multi-gigasample capture systems.
Designers should route LVDS outputs with 100 ohm differential impedance, keep analog and digital grounds separated until they join at the regulator, and provide solid low-ESL decoupling on all supply pins. The die-to-package thermal path of the LBGA-256 benefits from a stitched ground via array under the exposed pad to keep junction temperature within the industrial range.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB and signal-integrity design notes not always covered in the manufacturer's datasheet, making it a one-stop reference for engineers qualifying MAX109EHF-D into new and legacy designs.
Drop-in alternatives for MAX109EHF-D — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MAX109EHF-D (same form factor and footprint) — differing in Analog Input Bandwidth, Sample Rate, Resolution, Architecture, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MAX109EHF
✅ Drop-In📋 Reference alternative (not in catalog)
MAX108CHC-D
✅ Drop-In✓ In Stock
$128.5 / Unit
View Datasheet →MAX108CHC-B50105
✅ Drop-In✓ In Stock
$192 / Unit
View Datasheet →MAX1093BEEG
✅ Drop-In✓ In Stock
$4.3 / Unit
View Datasheet →MAX109EHF-D Maximum Ratings & Electrical Characteristics
| Resolution | 8 bit |
| Sample Rate | 2.2 Gsps |
| Number of Channels | 1 |
| Input Type | Differential (single-ended usable) |
| Full-Scale Input Range | 500 mV-P differential |
| Analog Input Bandwidth | 2.5 GHz |
| Track/Hold Amplifier | Integrated (on-die) |
| Output Format | LVDS, 1:4 demultiplexed |
| Number of LVDS Output Lanes | 4 (1:4 demux) |
| Per-Lane Output Data Rate | 550 MHz max |
| LVDS Supply Voltage | 3.0 V to 3.6 V |
| Analog Supply Voltages | +5 V and -5.2 V |
| Interleaving | Two-device 4.4 Gsps mode supported |
| Package | LBGA-256 (BALL) |
| Temperature Grade | Industrial |
| Mounting Type | Surface Mount (BGA) |
MAX109EHF-D lbga-256 (ball) Pin Configuration Guide
Pin configuration for MAX109EHF-D (lbga-256 (ball) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for MAX109EHF-D.
Refer to the datasheet for full pin configuration.
Typical Applications
MAX109EHF-D is suitable for 6 applications: Software-Defined Radio Direct-IF Digitization, Radar I/Q Baseband Digitizer, Digital Oscilloscope Front-End Channel, Broadband Communications Test Instrumentation, Medical Imaging Ultrasound Receiver, High-Speed Data Acquisition PCIe Card.
Software-Defined Radio Direct-IF Digitization
The MAX109EHF-D's 2.2 Gsps sample rate and 2.5 GHz analog input bandwidth enable direct sampling of IF stages up to 1 GHz without a preceding downconversion mixer, simplifying SDR receiver chains. The integrated track-and-hold reduces aperture jitter to sub-picosecond levels, preserving SNR on narrow-band signals where phase noise dominates. The 1:4 demultiplexed LVDS output at 550 MHz per lane routes directly into modern FPGA LVDS receivers, letting the FPGA implement the downstream channelizer, demodulator, and AGC in fabric. Designers typically place the ADC after a bandpass filter and a balun, then feed the LVDS lanes into a sync ISERDES block on a Xilinx 7-series or Lattice ECP5.
Recommended
Radar I/Q Baseband Digitizer
Wideband radar receivers use the MAX109EHF-D to digitize baseband or low-IF I/Q signals directly, capturing the full pulse bandwidth with 8-bit resolution at 2.2 Gsps. The integrated T/H preserves pulse fidelity, while the LVDS output demux keeps per-lane rates within FPGA LVDS capabilities, allowing pulse compression, MTI filtering, and CFAR detection in downstream DSP. Two MAX109 devices can be interleaved for 4.4 Gsps aggregate sampling, doubling instantaneous bandwidth for synthetic aperture and phased-array radar front ends. The part's industrial temperature grade suits field-deployed radar electronics in outdoor cabinets.
Recommended
Digital Oscilloscope Front-End Channel
Digital oscilloscope and wideband data-acquisition instrument designers use the MAX109EHF-D as the front-end ADC for 1 GHz-class bandwidth channels. The 2.2 Gsps sampling rate supports equivalent-time sampling on repetitive waveforms up to several GHz, and the on-chip T/H avoids the cost of an external sample-and-hold amplifier. The 1:4 LVDS demux feeds memory controller ASICs and FPGAs that buffer samples into deep acquisition memory before PCIe upload. The 8-bit resolution suits general-purpose lab oscilloscopes where vertical resolution matters less than bandwidth and update rate.
Recommended
Broadband Communications Test Instrumentation
Communications test gear such as vector signal analyzers, cable TV head-end monitoring, and DOCSIS / LTE baseband digitizers use the MAX109EHF-D for wideband capture of modulated carriers. The 500 mV-P differential input scales cleanly to typical 0 dBm RF front ends after an attenuator, and the 2.5 GHz bandwidth captures harmonics and intermodulation products for ACLR and EVM measurements. The LVDS outputs stream to an FPGA implementing the demodulator, equalizer, and measurement engine. Engineers typically combine the ADC with a wideband front-end balun and a programmable gain stage.
Recommended
Medical Imaging Ultrasound Receiver
Medical ultrasound systems digitize the received echoes at high rates to capture fine time-of-flight resolution for B-mode and Doppler imaging. The MAX109EHF-D's 2.2 Gsps sample rate allows direct sampling of up-converted IF echo signals without an analog mixer, and its integrated T/H preserves the fine phase information needed for Doppler shift measurement. The 1:4 demultiplexed LVDS output lets the beamforming FPGA capture multiple channels simultaneously, enabling parallel beamforming across hundreds of piezoelectric elements. Industrial temperature grade supports the chassis thermal environment of cart-based ultrasound systems.
Recommended
High-Speed Data Acquisition PCIe Card
Wideband PCIe data-acquisition cards use the MAX109EHF-D as the primary digitizer for one or two synchronized channels. The 2.2 Gsps rate captures gigahertz of instantaneous bandwidth for streaming to host memory over PCIe Gen3 x8, and the demultiplexed LVDS output routes cleanly to a host FPGA with internal SerDes. Designers add an external high-frequency clock and reference, then rely on the MAX109's integrated T/H for sub-picosecond aperture jitter. Such cards are widely used in physics experiments, spectrum monitoring, and broadband signal intelligence applications.
Recommended
Recommended Products Summary
Engineering reference data for MAX109EHF-D — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MAX109EHF | MAX108CHC-D | MAX108CHC-B50105 |
|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Package | LBGA-256 | LBGA-256 (same) | LBGA-256 (same) | LBGA-256 (same) |
| Sample Rate | 2.2 Gsps | 2.2 Gsps | 1.5 Gsps | 1.5 Gsps |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit |
| Output Interface | LVDS, 1:4 demux | LVDS, 1:4 demux | LVDS, 1:2 demux | LVDS, 1:2 demux |
| Integrated Track/Hold | Yes | Yes | Yes | Yes |
| Temperature Grade | Industrial | Commercial | Industrial | Industrial (custom screened) |
| Lifecycle Status | NRND | NRND | Active (legacy) | Active (custom) |
Key Differentiators
- Highest sample rate in the LBGA-256 Maxim 8-bit flash ADC family (vs MAX108CHC-D)
- 1:4 LVDS demux output for direct 550 MHz-per-lane FPGA capture (vs MAX108CHC-D)
- Industrial temperature grade variant explicitly ordered (vs MAX109EHF)
Design Notes
Route each MAX109EHF-D LVDS output lane as a 100 ohm differential pair with intra-pair skew under 25 ps and inter-lane length matching within 50 mil. Place 100 ohm differential terminations at the FPGA LVDS receiver pins, never at the ADC side. Keep a continuous ground reference plane beneath each pair to minimize crosstalk between adjacent lanes.
The MAX109EHF-D requires three separate supply rails (+5 V analog, -5.2 V analog, +3.3 V LVDS). Place 100 nF X7R ceramic decoupling within 2 mm of every supply pin, plus 10 uF bulk tantalum or ceramic capacitors near each rail entry. Use a star-ground topology so analog and digital grounds join only at the regulator return to avoid digital switching noise coupling into the input T/H.
Estimated: at maximum 2.2 Gsps with continuous LVDS switching into 100 ohm loads, the LBGA-256 power dissipation is approximately 2 W. With a typical LBGA theta-JA of 25 C/W on a 4-layer PCB and a 1 square-inch copper ground pad stitched with vias, junction rise is roughly 50 C above ambient - well within the industrial grade - but airflow or a heatsink is recommended in sealed enclosures.
Drive the analog input through a wideband balun (1:1 impedance ratio) or a differential amplifier with 100 ohm differential termination. Keep input traces short and matched to 50 ohm single-ended or 100 ohm differential controlled impedance. Maintain a continuous ground plane under the input traces; avoid routing digital LVDS lanes parallel to the analog input.
Compliance Information
Compliance status not confirmed in the verified distributor data - refer to the manufacturer datasheet ordering-information table and material declaration documents. Part is in NRND status; consult manufacturer for the latest environmental compliance certificates.
