MAX12558ETK+ - Dual 80Msps 14-Bit IF/Baseband ADC | Maxim Integrated
MPN: MAX12558ETK+ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.1 | $351.00 |
| 100 | $30.85 | $3,085.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $24.95 | $24,950.00 |
MAX12558ETK+ Overview
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog input voltages into discrete digital output codes, enabling digital signal processing of real-world signals. The MAX12558 belongs to the IF/baseband sampling ADC class, which sits architecturally between high-speed RF sampling ADCs (gigasample range) and general-purpose successive-approximation ADCs (kilosample range). Within the power-management and data-conversion IC taxonomy, IF-sampling ADCs like the MAX12558 are a sub-class of data converters -> ADC -> pipelined ADC -> mixed-signal IC -> semiconductor. They are typically used after downconversion stages in radio receivers and are valued for their combination of high sampling rate, moderate resolution (14-bit), low power consumption, and integrated T/H front ends that simplify front-end filter design.
Key features include dual simultaneous sampling at 80 Msps per channel, 14-bit resolution, integrated differential T/H inputs, an input bandwidth suitable for direct IF sampling up to 200 MHz, and CMOS-compatible digital outputs. The device operates from a single 3.3V analog supply and a separate 1.7V-3.6V digital supply, allowing direct connection to FPGAs, DSPs, or low-voltage ASICs without level shifting. Internal reference and clock-buffer circuits reduce external BOM.
The MAX12558 uses a multi-stage pipelined architecture with on-chip digital error correction, providing 14-bit linearity at 80 Msps with low latency per stage. The pipelined topology offers a favorable trade-off between sample rate, power consumption, and resolution for communications signal chains. The integrated T/H stage handles wideband differential inputs with high common-mode rejection, which is critical for digitizing noisy IF signals.
Typical applications include cellular base-station receiver digitizers, cable downstream receivers, radar IF processing, medical imaging digitizers, broadband communications test equipment, and multi-channel data-acquisition systems. The dual-channel architecture halves board area for I/Q or diversity receivers.
When designing with the MAX12558, ensure the analog input network is impedance-matched for the desired IF frequency and that the separate AVDD/DVDD rails are properly decoupled to prevent digital switching noise from coupling into the analog front end. The exposed pad on the TQFN-68 package must be soldered to a low-impedance ground plane for thermal dissipation and electrical performance.
This page synthesizes distributor pricing, drop-in package-compatible alternatives from the same Maxim family, and practical layout guidance not collected in any single manufacturer document.
Drop-in alternatives for MAX12558ETK+ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MAX12558ETK+ (same form factor and footprint) — differing in Resolution, Input Type, Function, Sample Rate, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MAX12558ETK+T
✅ Drop-In📋 Reference alternative (not in catalog)
MAX12558ETK+TD
✅ Drop-In✓ In Stock
$19.2 / Unit
View Datasheet →MAX12558ETK-D
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
AD9258BCPZ-80
✅ Drop-In📋 Reference alternative (not in catalog)
MAX12528ETK+
✅ Drop-In✓ In Stock
$24.85 / Unit
View Datasheet →MAX12558ETK+ Maximum Ratings & Electrical Characteristics
| Function | Dual 14-Bit Analog-to-Digital Converter |
| Resolution | 14 bit |
| Number of Inputs | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined |
| Sample Rate | 80 Msps (80,000 kSamples/s) |
| Input Type | Differential, wideband track-and-hold |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.7 V to 3.6 V |
| Digital Output Format | Two's complement or Gray code (pin-selectable) |
| Output Interface | CMOS-compatible, two parallel 14-bit buses |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Screening Level | Industrial |
| Package | 68-TQFN (10x10 mm, 0.80 mm height, MO-220WNND-2) |
| Number of Pins | 68 |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
MAX12558ETK+ 68-tqfn (10x10 mm, 0.80 mm height, mo-220wnnd-2) Pin Configuration Guide
Pin configuration for MAX12558ETK+ (68-tqfn (10x10 mm, 0.80 mm height, mo-220wnnd-2) package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for MAX12558ETK+.
Refer to the datasheet for full pin configuration.
Typical Applications
MAX12558ETK+ is suitable for 6 applications: Cellular Base-Station Receiver Digitizer, Cable Downstream Receiver, Radar IF Processing, Medical Imaging Digitizer, Broadband Communications Test Equipment, Multi-Channel Data Acquisition Systems.
Cellular Base-Station Receiver Digitizer
The MAX12558ETK+ is well-suited for digitizing intermediate-frequency (IF) signals in cellular base-station receivers. Its 80 Msps per-channel sampling on two simultaneous channels captures both I and Q paths from a single IF mixer, halving board area versus two discrete ADCs. The 14-bit resolution delivers the dynamic range needed for multi-carrier GSM/UMTS/LTE signals, and the wideband differential T/H inputs accept IF frequencies up to 200 MHz directly without an external downconversion stage. The separate 1.7V-3.6V digital supply interfaces directly to baseband FPGAs, removing level-shifters and reducing BOM.
Recommended
Cable Downstream Receiver
The MAX12558ETK+ fits DOCSIS downstream receiver digitizers, where a dual-channel ADC samples the downstream IF at 80 Msps per channel. The 14-bit resolution supports the modulation-error-ratio (MER) requirements for QAM downstream, while the integrated track-and-hold simplifies the front-end filter design between the tuner and the ADC. The CMOS output data format (two's complement or Gray code, pin-selectable) lets the designer optimize coding for either direct FPGA interfacing or pipelined DSP processing downstream.
Recommended
Radar IF Processing
In radar receiver signal chains, the MAX12558ETK+ serves as the IF digitizer after the radar front-end mixer. Dual-channel sampling at 80 Msps captures the I and Q baseband outputs of a quadrature demodulator, and the 14-bit resolution preserves dynamic range for moving-target-indicator (MTI) and pulse-Doppler processing. The wideband T/H supports pulsed radar IFs with fast settling, and the industrial -40 C to +85 C operating range tolerates outdoor or airborne equipment environments. The exposed pad on the TQFN-68 package must be soldered to a continuous ground plane for thermal dissipation under continuous sampling.
Recommended
Medical Imaging Digitizer
The MAX12558ETK+ is used in ultrasound and other medical imaging front ends to digitize the post-beamformer analog channels at 80 Msps with 14-bit resolution. The dual-channel architecture simultaneously samples two adjacent receive channels, keeping channel-to-channel skew minimal - critical for beamforming accuracy. The low-voltage CMOS outputs interface directly to image-processing FPGAs at 1.8V or 2.5V, and the differential inputs reject common-mode noise from the analog front end. Industrial temperature grade supports the regulated thermal environment of medical carts and rack-mounted imaging systems.
Recommended
Broadband Communications Test Equipment
Test and measurement instruments that analyze broadband communication signals - vector signal analyzers, modulation analyzers, and digitizers - rely on the MAX12558ETK+ to capture IF signals with sufficient bandwidth and dynamic range. The 80 Msps sampling rate satisfies analysis bandwidth requirements for many cellular and Wi-Fi waveforms, and the dual channels enable simultaneous capture of reference and device-under-test signals for comparison. The pin-selectable two's complement or Gray code output simplifies synchronization in trigger and capture logic downstream.
Recommended
Multi-Channel Data Acquisition Systems
Multi-channel data acquisition (DAQ) cards in industrial automation and instrumentation use the MAX12558ETK+ as the per-channel ADC, leveraging its dual simultaneous sampling to double channel density per PCB. The 14-bit resolution covers most industrial sensor signal ranges, and the 80 Msps rate accommodates vibration analysis, sonar, and other wideband transducer signals. The split analog/digital supply rails isolate noisy digital return currents from sensitive analog input stages, and the TQFN-68 package with exposed pad provides a compact footprint with good thermal performance for high channel-count boards.
Recommended
Recommended Products Summary
Engineering reference data for MAX12558ETK+ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MAX12558ETK+T | MAX12558ETK+TD | MAX12558ETK-D | AD9258BCPZ-80 | MAX12528ETK+ |
|---|---|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Analog Devices | Maxim Integrated |
| Package | TQFN-68 (10x10 mm) | TQFN-68 (10x10 mm) - same | TQFN-68 (10x10 mm) - same | TQFN-68 (10x10 mm) - same | TQFN-68 (10x10 mm) - same | TQFN-68 (10x10 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit |
| Sample Rate | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 80 Msps |
| Number of Channels | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Supply Range | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V |
| Output Format | CMOS, two's complement or Gray code | CMOS, two's complement or Gray code | CMOS, two's complement or Gray code | CMOS, two's complement or Gray code | CMOS, two's complement or Gray code | CMOS, two's complement or Gray code |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Dual-channel simultaneous sampling at 80 Msps in compact 68-TQFN footprint (vs MAX12528ETK+)
- Split analog/digital supply rails for direct FPGA interfacing (vs AD9258BCPZ-80)
- Pin-selectable two's complement or Gray code output format (vs Generic 14-bit ADC competitors)
Design Notes
Place the analog input network (differential driver, anti-aliasing filter, and coupling capacitors) as close to the IN_A+/IN_A- and IN_B+/IN_B- pins as possible. Route the differential pair with matched impedance (typically 100 ohm differential) and keep the pair tightly coupled over its entire length to preserve common-mode rejection. The TQFN-68 exposed pad must be soldered to a continuous low-impedance ground plane to provide both thermal dissipation and a stable reference for the input T/H stage. Avoid routing digital output traces under or adjacent to the analog input pins to minimize capacitive coupling.
Use separate analog (AVDD) and digital (DVDD) supply planes tied together at a single point near the ADC's supply pins, with 0.1 uF and 10 uF decoupling capacitors on every supply pin. The split-rail architecture is a key benefit of the MAX12558 - keep the digital return currents isolated from the analog input stage return. A ferrite bead between the analog and digital supplies can further reduce switching-noise coupling in noisy environments.
Do not omit the input common-mode bias voltage; the MAX12558 differential inputs require an external common-mode reference (typically AVDD/2 generated by a low-noise op-amp or resistor divider) to set the input operating point. Floating inputs can saturate the T/H and produce invalid codes. Also confirm the output data format selection (two's complement vs Gray code) matches the downstream FPGA or DSP capture logic before layout freeze - format selection is pin-strapped and cannot be changed in software.
The CMOS output bus transitions at high speed (80 Msps x 14 bits per channel = 1.12 Gbps aggregate). Match the length of each output bit to within ~1 mm to minimize skew, and use a 22 ohm to 33 ohm series-termination resistor near the ADC output pins to damp reflections on the FPGA-side traces. Place a ground reference plane directly under the output traces to control impedance. If the FPGA is more than 50 mm away, consider buffering the outputs with low-skew clock-driver ICs.
Compliance Information
RoHS compliant per Maxim Integrated product page (the '+' suffix in the part number denotes RoHS-compliant lead-free finish). Industrial temperature screening only - not AEC-Q100 qualified. REACH compliance not explicitly stated in the provided data; conflict minerals compliance per Maxim standard policy.
