MAX1428ETN+TD - 15-Bit 80Msps IF ADC | Maxim Integrated
MPN: MAX1428ETN+TD ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $19.5 | $19.50 |
| 10 | $17.85 | $178.50 |
| 100 | $15.2 | $1,520.00 |
| 500 | $12.95 | $6,475.00 |
| 1,000 | $10.4 | $10,400.00 |
MAX1428ETN+TD Overview
An ADC is a mixed-signal data converter that samples a continuous analog input voltage and quantizes it into a discrete digital code at a defined sample rate. High-speed pipeline ADCs such as the MAX1428 sit in the hierarchy of analog-to-digital converters -> data converters -> mixed-signal ICs -> semiconductors. The MAX1428 specifically targets the IF-sampling use case where a wideband analog signal at tens to hundreds of MHz must be captured directly, eliminating a second down-conversion stage in the receiver chain.
Key performance figures include a guaranteed 80 Msps minimum sample rate, 73.9 dB SNR at fIN = 70 MHz and AIN = -2 dBFS, 83 dBc/91 dBc single-tone SFDR1/SFDR2 at the same input, -82 dB multitone SFDR for two tones at 69 MHz and 71 MHz, and exceptional aperture jitter below 0.25 ps that preserves dynamic performance at high analog input frequencies. The converter's noise floor of -78.4 dBFS gives the receiver chain enough dynamic range for sensitive demodulation.
Architecturally, the part uses a pipelined multi-stage converter core with proprietary digital error correction, an internal bandgap reference, and a fully differential analog input path that improves common-mode rejection and harmonic performance. The +TD tape-and-reel packaging supports automated pick-and-place on high-density RF/IF receiver boards.
Typical end uses include cellular base-station IF digitizers, software-defined radio receivers, broadband cable head-end equipment, spectrum analyzer acquisition channels, and medical ultrasound beamformers. Anywhere an analog signal in the 50 MHz to 200 MHz band needs direct digitization with high spurious-free dynamic range, the MAX1428 is a viable candidate.
When designing with the MAX1428, supply a low-noise analog front-end to preserve the part's dynamic range; the 0.25 ps aperture jitter spec will only deliver the rated SNR if the input driver keeps the right ADC cleaner than the ADC's own internal noise. Decouple AVDD and DVDD with separate 0.1 uF ceramic capacitors placed as close to the pins as possible.
This page synthesizes distributor pricing, parametric drop-in equivalents, and dynamic-performance design notes that go beyond the headline numbers in the manufacturer datasheet.
Drop-in alternatives for MAX1428ETN+TD — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MAX1428ETN+TD (same form factor and footprint) — differing in Architecture, Noise Floor, Terminal Form.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MAX1428ETN+D
✅ Drop-In📋 Reference alternative (not in catalog)
MAX1427ETN+TD
✅ Drop-In📋 Reference alternative (not in catalog)
MAX1418ETN+TD
✅ Drop-In📋 Reference alternative (not in catalog)
MAX1430ETN+TD
✅ Drop-In📋 Reference alternative (not in catalog)
MAX1428ETN+TD Maximum Ratings & Electrical Characteristics
| Resolution | 15 bit |
| Sample Rate (Minimum) | 80 Msps |
| Architecture | Pipelined ADC |
| Noise Floor | -78.4 dBFS |
| SNR at fIN = 70 MHz, AIN = -2 dBFS | 73.9 dB |
| Single-Tone SFDR1 at fIN = 70 MHz | 83 dBc |
| Single-Tone SFDR2 at fIN = 70 MHz | 91 dBc |
| Multitone SFDR (fIN = 69/71 MHz) | -82 dB |
| Aperture Jitter | < 0.25 ps |
| Number of Terminals | 56 |
| Terminal Form | No Lead (HVQCCN) |
| Package Code | HVQCCN |
| Package Shape | Square |
| Temperature Grade | Industrial |
| Packaging | Tape & Reel (+TD suffix) |
| Target Application | IF Sampling / Wideband Digitization |
MAX1428ETN+TD Pin Configuration
| Pin 1 | AVDD — Analog supply voltage |
| Pin 2 | IN+ — Differential analog input (positive) |
| Pin 3 | IN- — Differential analog input (negative) |
| Pin 4 | CM — Common-mode voltage bypass |
| Pin 5 | REFP — Positive reference decoupling |
| Pin 6 | REFN — Negative reference decoupling |
| Pin 7 | GND — Analog ground |
| Pin 8 | NC — Not connected (per datasheet) |
| Pin 9 | CLK — Clock input |
| Pin 10 | CLKB — Complementary clock input |
| Pin 11 | AVDD — Analog supply voltage |
| Pin 12 | DVDD — Digital supply voltage |
| Pin 13 | DGND — Digital ground |
| Pin 14 | D0-P — LVDS digital output bit 0 (positive) |
| Pin 15 | D0-N — LVDS digital output bit 0 (negative) |
| Pin 16 | D1-P — LVDS digital output bit 1 (positive) |
| Pin 17 | D1-N — LVDS digital output bit 1 (negative) |
| Pin 18 | D2-P — LVDS digital output bit 2 (positive) |
| Pin 19 | D2-N — LVDS digital output bit 2 (negative) |
| Pin 20 | D3-P — LVDS digital output bit 3 (positive) |
| Pin 21 | D3-N — LVDS digital output bit 3 (negative) |
| Pin 22 | D4-P — LVDS digital output bit 4 (positive) |
| Pin 23 | D4-N — LVDS digital output bit 4 (negative) |
| Pin 24 | D5-P — LVDS digital output bit 5 (positive) |
| Pin 25 | D5-N — LVDS digital output bit 5 (negative) |
| Pin 26 | D6-P — LVDS digital output bit 6 (positive) |
| Pin 27 | D6-N — LVDS digital output bit 6 (negative) |
| Pin 28 | D7-P — LVDS digital output bit 7 (positive) |
| Pin 29 | D7-N — LVDS digital output bit 7 (negative) |
| Pin 30 | D8-P — LVDS digital output bit 8 (positive) |
| Pin 31 | D8-N — LVDS digital output bit 8 (negative) |
| Pin 32 | D9-P — LVDS digital output bit 9 (positive) |
| Pin 33 | D9-N — LVDS digital output bit 9 (negative) |
| Pin 34 | D10-P — LVDS digital output bit 10 (positive) |
| Pin 35 | D10-N — LVDS digital output bit 10 (negative) |
| Pin 36 | D11-P — LVDS digital output bit 11 (positive) |
| Pin 37 | D11-N — LVDS digital output bit 11 (negative) |
| Pin 38 | D12-P — LVDS digital output bit 12 (positive) |
| Pin 39 | D12-N — LVDS digital output bit 12 (negative) |
| Pin 40 | D13-P — LVDS digital output bit 13 (positive) |
| Pin 41 | D13-N — LVDS digital output bit 13 (negative) |
| Pin 42 | D14-P — LVDS digital output bit 14 (positive) |
| Pin 43 | D14-N — LVDS digital output bit 14 (negative) |
| Pin 44 | OVR-P — LVDS out-of-range flag (positive) |
| Pin 45 | OVR-N — LVDS out-of-range flag (negative) |
| Pin 46 | DCO-P — LVDS data clock output (positive) |
| Pin 47 | DCO-N — LVDS data clock output (negative) |
| Pin 48 | FCO-P — LVDS frame clock output (positive) |
| Pin 49 | FCO-N — LVDS frame clock output (negative) |
| Pin 50 | AVDD — Analog supply voltage |
| Pin 51 | GND — Analog ground |
| Pin 52 | REFIN — External reference input |
| Pin 53 | REFOUT — Internal reference output |
| Pin 54 | PD — Power-down control |
| Pin 55 | MODE — Output mode / test configuration |
| Pin 56 | EP — Exposed thermal pad (connect to GND) |
Typical Applications
MAX1428ETN+TD is suitable for 6 applications: Cellular Base-Station IF Digitization, Software-Defined Radio Receivers, Broadband Cable Head-End Equipment, Spectrum Analyzer Acquisition Channel, Medical Ultrasound Beamformer Receivers, Industrial Radar and Lidar Digitization.
Cellular Base-Station IF Digitization
The MAX1428ETN+TD is well matched to direct IF sampling in cellular base-station receivers, where the antenna chain converts RF to an intermediate frequency and the MAX1428's -78.4 dBFS noise floor plus 73.9 dB SNR at 70 MHz cleanly capture the modulation bandwidth. Its 0.25 ps aperture jitter preserves SNR even at high IF frequencies, allowing elimination of a second down-conversion stage and reducing overall BOM. Place the part after the final IF SAW filter with a low-noise ADC driver; the wideband analog input rejects in-band interferers and the digital outputs stream into an FPGA for downstream demodulation.
Recommended
Software-Defined Radio Receivers
Software-defined radio (SDR) platforms benefit from the MAX1428ETN+TD's 80 Msps sample rate combined with -78.4 dBFS noise floor, which lets the SDR capture tens of MHz of spectrum bandwidth at once and down-convert in software. The 83 dBc SFDR1 and 91 dBc SFDR2 at 70 MHz input ensure spurious responses stay below the noise floor of typical SDR demodulators, while the 56-pin HVQCCN package keeps the analog front-end compact for embedded or portable SDR modules. The wideband digital outputs map to standard LVDS interfaces used in modern FPGA-based SDR boards.
Recommended
Broadband Cable Head-End Equipment
In cable head-end and distribution infrastructure, the MAX1428ETN+TD digitizes wideband downstream signals after the IF stage, where the -78.4 dBFS noise floor is critical for low bit-error-rate demodulation of dense QAM constellations. Its 73.9 dB SNR at 70 MHz input directly translates to higher modulation-order support and improved channel capacity per port. Use the part with a low-noise IF amplifier and anti-alias filter; the wide input bandwidth preserves modulation fidelity and the LVDS digital outputs interface to downstream FPGAs.
Recommended
Spectrum Analyzer Acquisition Channel
Test and measurement spectrum analyzers require wideband, high-SFDR digitizers, and the MAX1428ETN+TD delivers 83 dBc/91 dBc single-tone SFDR and 0.25 ps aperture jitter for accurate IF analysis. With -78.4 dBFS noise floor and 73.9 dB SNR at 70 MHz, the part reliably captures weak signals adjacent to strong tones - the classic spectrum analyzer dynamic-range requirement. The HVQCCN-56 package suits dense analyzer front-end boards, while LVDS digital outputs ease timing closure on the FPGA capture stage.
Recommended
Medical Ultrasound Beamformer Receivers
Medical ultrasound systems use IF-sampling ADCs to digitize time-gain-compensated echo signals, and the MAX1428ETN+TD's 80 Msps rate plus 73.9 dB SNR support the wide dynamic range required for harmonic imaging. The -78.4 dBFS noise floor lets the beamformer preserve subtle echoes that distinguish tissue types, while 0.25 ps aperture jitter keeps the time-of-arrival accuracy needed for fine beam-steering. The HVQCCN-56 package fits into the compact channel boards used in multi-element ultrasound probes.
Recommended
Industrial Radar and Lidar Digitization
Industrial FMCW radar and Lidar systems use the MAX1428ETN+TD to digitize IF signals from the radar mixer chain, where the 0.25 ps aperture jitter preserves range resolution and the -78.4 dBFS noise floor enables detection of weak returns. The 80 Msps sample rate captures chirp bandwidths used in sub-meter industrial ranging, and 73.9 dB SNR at 70 MHz input preserves object-plane accuracy. The compact HVQCCN-56 package supports high-density channel cards typical of phased-array industrial radar front-ends.
Recommended
Recommended Products Summary
Engineering reference data for MAX1428ETN+TD — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MAX1428ETN+D | MAX1427ETN+TD | MAX1418ETN+TD | MAX1430ETN+TD |
|---|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Package | HVQCCN-56 (TQFN-style) | HVQCCN-56 - same | HVQCCN-56 - same | HVQCCN-56 - same | HVQCCN-56 - same |
| Temperature Grade | Industrial | Industrial | Industrial | Industrial | Industrial |
| Packaging Form | Tape & Reel (+TD) | Tray (+D) | Tape & Reel (+TD) | Tape & Reel (+TD) | Tape & Reel (+TD) |
Key Differentiators
- Highest dynamic range in the 15-bit 80 Msps Maxim ADC family (vs MAX1427ETN+TD)
- Sub-picosecond aperture jitter preserves SNR at high IF (vs MAX1418ETN+TD)
- Compact HVQCCN-56 package for dense IF receiver boards (vs MAX1430ETN+TD)
Design Notes
Preserve SNR at IF frequencies by using an ADC driver with sub-ps jitter and keeping clock traces length-matched with controlled impedance. The MAX1428ETN+TD's 0.25 ps aperture jitter can only deliver the rated 73.9 dB SNR at 70 MHz if the analog front-end and clock path do not add jitter of their own. Recommended: use a low-jitter clock source such as a VCXO or dedicated clock generator and route CLK/CLKB as a 100 ohm differential pair.
Decouple AVDD and DVDD with separate 0.1 uF ceramic capacitors placed as close to the supply pins as possible. Add a 10 uF bulk capacitor on each rail. The MAX1428ETN+TD's -78.4 dBFS noise floor is only achievable when the analog supply is clean; a switching regulator on AVDD will degrade SNR measurably. Use an LDO or low-noise linear regulator for the AVDD rail.
Route the LVDS output pairs (D0..D14, OVR, DCO, FCO) as length-matched 100 ohm differential pairs to minimize skew. Keep the analog input traces short and symmetric around the differential pair IN+/IN- to preserve the 83 dBc/91 dBc SFDR. Connect the exposed pad (pin 56) to a clean analog ground plane to keep junction temperature within the industrial range.
Do not route digital outputs beneath the analog input traces on adjacent layers - coupling from the LVDS edges will degrade SFDR. Do not share the same ferrite between AVDD and DVDD; the noise on the digital rail will couple into the analog input through the ferrout. Do not exceed the AVDD absolute-maximum voltage (per datasheet) - the input protection will not survive transients beyond the rated limit.
Compliance Information
RoHS and REACH compliant per Maxim Integrated / Analog Devices product page. Not AEC-Q100 qualified - industrial temperature grade only.
