MC68360ZQ25VL - 25MHz QUICC 32-Bit MPU 357-BGA | NXP
MPN: MC68360ZQ25VL ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $129.55 | $129.55 |
| 10 | $116.6 | $1,166.00 |
| 100 | $103.64 | $10,364.00 |
| 250 | $95 | $23,750.00 |
| 500 | $88.5 | $44,250.00 |
| 1,000 | $81.25 | $81,250.00 |
MC68360ZQ25VL Overview
What is a QUICC microcontroller? A QUICC (Quad Integrated Communication Controller) is a category of integrated microprocessor + peripheral combination IC that pairs a CPU core with multiple communication protocol engines, allowing the chip to handle serial protocol framing (HDLC, UART, BISYNC, transparent, Ethernet) without burdening the CPU. The MC68360 sits in the broader hierarchy of MPU > 32-bit microprocessor > ColdFire/CPU32+ family > communication controller IC > semiconductor. QUICC devices are a defining category of Freescale/NXP legacy telecom silicon and remain in use in long-lifecycle industrial equipment, telecom backplanes, and protocol-bridging designs.
Key features of the MC68360ZQ25VL include four serial communication controllers, an SPI/I2C-compatible serial interface, a 32-bit CPU32+ core at 25 MHz, eight 16-bit timers, and a flexible system integration unit with chip selects and interrupt controllers. The QUICC CPM coprocessor offloads serial processing, leaving the CPU free for control-plane tasks, while the on-chip memory map supports DRAM, SRAM, and ROM external memories with wait-state configuration.
Architecturally, the part combines a 32-bit CPU32+ core (M68000-family ISA) with a separate RISC-based communications processor module (CPM) that contains the SCCs, SMCs, and a serial DMA controller. The two-processor internal structure allows deterministic serial throughput independent of CPU load, a key reason this family persists in protocol-bridging telecom designs.
Typical applications include industrial telecom controllers, legacy WAN routers, serial-protocol bridges (HDLC/async), industrial automation backplanes, POS and ATM/frame-relay edge nodes, and any long-lifecycle system originally designed around the QUICC platform. The wide integration of peripherals reduces board area and BOM versus discrete processor+comm-controller designs.
When designing with this part, note that it is pinned out as a 357-ball PBGA requiring careful PCB stack-up and controlled-impedance routing for the parallel memory bus, and that several variants in the MC68360 family share the same package but differ in frequency, RAM configuration, or Ethernet presence. Designers should verify the exact suffix (ZQ25VL, VR25VL, CAI25L) against the system clock and peripheral requirements before reusing an existing layout. This page synthesizes distributor pricing, same-family drop-in alternatives, and protocol-controller design notes not found in any single manufacturer datasheet.
Drop-in alternatives for MC68360ZQ25VL — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68360ZQ25VL (same form factor and footprint) — differing in Core Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68360VR25VL
✅ Drop-In📋 Reference alternative (not in catalog)
MC68360CAI25L
✅ Drop-In✓ In Stock
$23.95 / Unit
View Datasheet →MC68EN360CVR25L
✅ Drop-In📋 Reference alternative (not in catalog)
MC68360ZQ25VL Maximum Ratings & Electrical Characteristics
| Core Architecture | CPU32+ (M68000-family) |
| Core Count | 1 |
| Data Bus Width | 32-Bit |
| Maximum Clock Frequency | 25 MHz |
| Process Technology | 0.57 um CMOS |
| Serial Communication Controllers (SCC) | 4 |
| Serial Interface Module (SIM) | Yes (SPI/I2C-capable) |
| Timers | 8 x 16-bit |
| Package | 357-PBGA (25x25 mm) |
| Mounting Type | Surface Mount |
| Terminal Form | Ball |
| Number of Terminals | 357 |
| Package Shape | Square |
MC68360ZQ25VL Pin Configuration
| Pin A1 | [DATA_NEEDED] — Per datasheet BGA map; ball group allocation documented in MC68360 reference manual |
| Pin BALL-NUMBERED | [DATA_NEEDED: full 357-pin table] — Full BGA ballmap (data bus, address bus, SCC, SIM, timers, supply, NC) is provided in the NXP datasheet; full per-ball list omitted here to avoid fabrication. Consult the official MC68360 datasheet for the complete 357-ball PBGA table. |
Typical Applications
MC68360ZQ25VL is suitable for 6 applications: Industrial Telecom Controllers, Legacy WAN Router Bridges, HDLC/Async Protocol Bridges, Industrial Automation Backplanes, POS and ATM/Frame-Relay Edge Nodes, Long-Lifecycle Protocol Converter Systems.
Industrial Telecom Controllers
The MC68360ZQ25VL's CPM-based protocol offload and four SCCs make it ideal for legacy and long-lifecycle telecom control boards (T1/E1 framer bridges, channel banks, PBX backplanes). Its 25 MHz CPU32+ core handles control-plane housekeeping while the four SCCs run HDLC or async channels deterministically at line rate. The 357-BGA 25x25 mm package concentrates the entire CPU plus comms subsystem on one device, replacing what would otherwise be a discrete processor-plus-comm-controller pair. Engineers reusing this part benefit from the wide ecosystem of MC68360 reference designs still circulating in telecom ODM archives.
Recommended
Legacy WAN Router Bridges
For WAN routers and protocol-bridging appliances originally designed around the QUICC platform, the MC68360ZQ25VL pins out the same 357-ball BGA and runs the same CPM firmware as its peers, allowing direct PCB reuse. Its 4 SCCs handle multiple WAN serial links while the CPU32+ runs routing/control tasks. The 25 MHz speed is appropriate for low-to-mid throughput legacy WAN bridges (sub-10 Mbps aggregate) where determinism and protocol maturity matter more than raw compute.
Recommended
HDLC/Async Protocol Bridges
Each SCC of the MC68360ZQ25VL supports HDLC/SDLC, UART, BISYNC, and transparent bit-stream protocols in hardware, with the CPM providing DMA and framing on the chip. This makes the part a strong fit for protocol-bridging gateways that need to translate between async serial, sync HDLC, and BISYNC streams without CPU overhead. The 8 x 16-bit timers support bit-clock generation for legacy sync links, and the 25 MHz CPU is adequate to supervise routing while the SCCs move data.
Recommended
Industrial Automation Backplanes
In factory automation backplanes where long product lifecycles (15-25 years) intersect with deterministic serial comms, the MC68360ZQ25VL fits as a serial-master controller that talks RS-485/HDLC to field devices via its SCCs and SPI peripherals. Its external memory bus (parallel, 32-bit) ties directly to SRAM/DRAM and supports boot from ROM with wait-state configuration. Designers value the deterministic CPM offload for sub-millisecond fieldbus response times on legacy protocols.
Recommended
POS and ATM/Frame-Relay Edge Nodes
POS terminals, ATM concentrators, and frame-relay edge nodes that run HDLC over legacy WAN ports can place the MC68360ZQ25VL at the serial aggregation point, using the CPM to handle per-link framing and the CPU32+ for transaction processing. The 357-BGA package integrates CPU, comm controllers, and timers in one footprint, shrinking the BOM versus processor-plus-serial-chip designs. The 25 MHz clock and 0.57 um process favor low power over absolute throughput, ideal for distributed edge nodes.
Recommended
Long-Lifecycle Protocol Converter Systems
Equipment vendors who must support a deployed base for decades - railway signaling, energy SCADA, defense sub-systems - often select the MC68360ZQ25VL because its lifecycle overlaps with their installed systems and the CPM is well understood to engineering teams. The 357-BGA pinout supports a single PCB layout across multiple MC68360 suffixes, simplifying second-source decisions. The 0.57 um CMOS process yields robust operation over industrial temperature ranges when paired with the appropriate device grade.
Recommended
Recommended Products Summary
Engineering reference data for MC68360ZQ25VL — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68360VR25VL | MC68360CAI25L | MC68EN360CVR25L |
|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same |
| Core | CPU32+ (32-bit) | CPU32+ (32-bit) | CPU32+ (32-bit) | CPU32+ (32-bit) |
| Clock Frequency | 25 MHz | 25 MHz | 25 MHz | 25 MHz |
| SCC Count | 4 | 4 | 4 | 4 |
| Ethernet MAC | No | No (verify per suffix) | No (verify per suffix) | Yes (10/100 Ethernet) |
| Process | 0.57 um CMOS | 0.57 um CMOS | 0.57 um CMOS | 0.57 um CMOS |
| Lifecycle | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
Key Differentiators
- Combined CPU + CPM coprocessor on a single die (vs MC68302EH20C)
- Ethernet-enabled sibling in same footprint (vs MC68EN360CVR25L)
- 357-ball PBGA integrates entire comm subsystem (vs Discrete CPU + external UART/SCC chip)
Design Notes
The 357-ball PBGA at 25x25 mm demands a multilayer PCB stack-up with power planes adjacent to the BGA and matched-impedance routing for the 32-bit external memory bus. Use 6+ layer stack-up with a dedicated ground plane under the BGA and matched-length nets for data/address/strobe. Place 0.1uF decoupling caps on every VDD/VSS pair adjacent to the BGA, plus bulk 10-22uF tantalums near the power pins. The high pin density prohibits dog-bone fanout - recommend microvia-in-pad with sub-0.5 mm pitch breakout.
At 0.57 um CMOS process and 25 MHz clock the device is not a thermal hotspot, but the 357-BGA still concentrates heat at the die. Provide a contiguous ground/thermal plane directly under the PBGA with thermal vias to the bottom layer. Keep the device away from heat-generating analog line drivers. If designing for sealed enclosure, size the ground plane to spread waste heat over the board area rather than local to the BGA.
Several same-package, same-speed MC68360 suffixes exist (ZQ25VL, VR25VL, CAI25L, EN360 variants). They share the same 357-ball footprint and 25 MHz core but differ in feature-mask (Ethernet, RAM size, peripheral enable). Do NOT substitute across suffixes without cross-referencing the peripheral-enable registers and ball-map tables in the datasheet - some balls are repurposed between variants. After cold boot, always read the chip's ID register (or equivalent) to confirm the expected suffix is mounted, otherwise code paths using absent peripherals will hang.
The CPM offloads serial DMA, but the parallel memory bus still runs at the 25 MHz CPU clock (with possible external bus stretching). Series-terminate address and data nets at the driver if bus lengths exceed 50 mm; add 22-33 ohm resistors near the BGA. Place external SRAM/DRAM close to the BGA, with ground-guard vias around clock signals to control crosstalk. For SCC serial I/O, keep trace lengths short and use controlled-impedance routing if running above a few Mbps.
Compliance Information
Datasheet published 1995-06-07 per FindIC; pre-dates widespread RoHS documentation. Authoritative compliance values not present in verified web data - set to 'unknown' rather than fabricate.
