MC68SEC000AE20 - 20MHz Static 32-bit MPU, 64-LQFP | NXP Semiconductors
MPN: MC68SEC000AE20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.4 | $7,400.00 |
MC68SEC000AE20 Overview
A microprocessor (MPU) is a CPU-centric integrated circuit that requires external memory (RAM, ROM/Flash) and peripheral glue logic to form a complete computer system, in contrast to a microcontroller (MCU) which integrates memory and peripherals on-chip. The MC68SEC000 sits in the M68K family hierarchy: EC000 -> MC68000 -> ColdFire -> modern Power Architecture, with each generation preserving software compatibility at the instruction-set level. As a member of the power management / processing category, this static MPU enables low-power designs in industrial control, automotive, and embedded systems where deterministic clock gating is required.
Key features of the MC68SEC000AE20 include 32-bit internal data paths, a 24-bit address bus (16 MB linear address space), a 16-bit external data bus, eight 32-bit general-purpose data registers, seven 32-bit address registers, six internal interrupt levels plus a non-maskable interrupt, a static CMOS process for low quiescent current, and TTL-compatible I/O. The 20 MHz clock rate sustains approximately 2 MIPS of sustained throughput for typical instruction mixes, while full static operation allows designers to halt the clock in sleep mode to minimize power in battery-backed applications.
Architecturally, the MC68SEC000 uses a microcoded M68K instruction pipeline with prefetch and bus arbitration logic, supporting vectored autovector interrupts, supervisor/user privilege levels, and Motorola peripheral bus cycles. Compared with the original MC68000, the SEC000 variant retains software compatibility while adding fully-static operation, allowing clock frequencies to be reduced to DC for true standby. Compared with the original CMOS MC68HC000, the SEC000 further trims power by removing dynamic refresh requirements, making it suitable for portable or solar-powered embedded products.
Typical applications include industrial automation controllers, point-of-sale terminals, medical instrumentation front-ends, automotive body and chassis ECUs (with external watchdog), legacy 16-bit bus peripheral hubs, and educational microprocessor training platforms. The 64-LQFP package also makes the part straightforward to assemble on standard SMT lines and rework on existing 68SEC000 designs.
When designing with the MC68SEC000AE20, ensure that asynchronous bus cycles are correctly terminated and that the static clock can be gated in software or via an external power-management controller to take full advantage of the device's low-power standby capability. Pairing the MPU with a TTL bus transceivers and a hardware watchdog supervisor is recommended for safety-critical applications.
This page synthesizes distributor stock, pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for MC68SEC000AE20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68SEC000AE20 (same form factor and footprint) — differing in Address Bus Width, Data Bus Width, Internal Registers, Interrupt Levels, Maximum Clock Frequency.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68SEC000AE10
✅ Drop-In📋 Reference alternative (not in catalog)
MC68SEC000AE16
✅ Drop-In✓ In Stock
$15.95 / Unit
View Datasheet →MC68SEC000AE20R
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MC68EC000AE20
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MC68HC000AE20
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MC68SEC000AE20
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →MC68SEC000AE20 Maximum Ratings & Electrical Characteristics
| Core | M680x0 EC000 |
| Number of Cores | 1 |
| Data Bus Width | 32-bit (16-bit external) |
| Instruction Set Architecture | M68K / 68000 family |
| Maximum Clock Frequency | 20 MHz |
| Operating Voltage | 5 V |
| Address Bus Width | 24-bit (16 MB address space) |
| Operating Mode | Static (clock may be halted to DC) |
| Internal Registers | 8 x 32-bit data + 7 x 32-bit address |
| Interrupt Levels | 6 internal + 1 NMI (7 total) |
| Package | 64-LQFP (10x10 mm) |
| Mounting Type | Surface Mount |
| Process Technology | CMOS |
MC68SEC000AE20 Pin Configuration
| Pin 1 | VCC — +5V power supply |
| Pin 2 | D8 — Data bus bit 8 |
| Pin 3 | D9 — Data bus bit 9 |
| Pin 4 | D10 — Data bus bit 10 |
| Pin 5 | D11 — Data bus bit 11 |
| Pin 6 | D12 — Data bus bit 12 |
| Pin 7 | D13 — Data bus bit 13 |
| Pin 8 | D14 — Data bus bit 14 |
| Pin 9 | D15 — Data bus bit 15 |
| Pin 10 | GND — Ground |
| Pin 11 | A1 — Address bus bit 1 |
| Pin 12 | A2 — Address bus bit 2 |
| Pin 13 | A3 — Address bus bit 3 |
| Pin 14 | A4 — Address bus bit 4 |
| Pin 15 | A5 — Address bus bit 5 |
| Pin 16 | A6 — Address bus bit 6 |
| Pin 17 | A7 — Address bus bit 7 |
| Pin 18 | A8 — Address bus bit 8 |
| Pin 19 | A9 — Address bus bit 9 |
| Pin 20 | A10 — Address bus bit 10 |
| Pin 21 | A11 — Address bus bit 11 |
| Pin 22 | A12 — Address bus bit 12 |
| Pin 23 | A13 — Address bus bit 13 |
| Pin 24 | A14 — Address bus bit 14 |
| Pin 25 | A15 — Address bus bit 15 |
| Pin 26 | A16 — Address bus bit 16 |
| Pin 27 | A17 — Address bus bit 17 |
| Pin 28 | A18 — Address bus bit 18 |
| Pin 29 | A19 — Address bus bit 19 |
| Pin 30 | A20 — Address bus bit 20 |
| Pin 31 | A21 — Address bus bit 21 |
| Pin 32 | A22 — Address bus bit 22 |
| Pin 33 | A23 — Address bus bit 23 |
| Pin 34 | GND — Ground |
| Pin 35 | AS — Address Strobe (active low) |
| Pin 36 | UDS — Upper Data Strobe (active low) |
| Pin 37 | LDS — Lower Data Strobe (active low) |
| Pin 38 | R/W — Read/Write (1=Read, 0=Write) |
| Pin 39 | DTACK — Data Transfer Acknowledge (active low) |
| Pin 40 | BR — Bus Request (active low) |
| Pin 41 | BG — Bus Grant (active low) |
| Pin 42 | BGACK — Bus Grant Acknowledge (active low) |
| Pin 43 | FC0 — Function Code bit 0 |
| Pin 44 | FC1 — Function Code bit 1 |
| Pin 45 | FC2 — Function Code bit 2 |
| Pin 46 | IPL0 — Interrupt Priority Level bit 0 |
| Pin 47 | IPL1 — Interrupt Priority Level bit 1 |
| Pin 48 | IPL2 — Interrupt Priority Level bit 2 |
| Pin 49 | CLK — Clock input |
| Pin 50 | GND — Ground |
| Pin 51 | RESET — Reset (active low) |
| Pin 52 | HALT — Halt (active low) |
| Pin 53 | E — Enable clock output (E clock) |
| Pin 54 | VPA — Valid Peripheral Address (active low) |
| Pin 55 | VMA — Valid Memory Address (active low) |
| Pin 56 | D0 — Data bus bit 0 |
| Pin 57 | D1 — Data bus bit 1 |
| Pin 58 | D2 — Data bus bit 2 |
| Pin 59 | D3 — Data bus bit 3 |
| Pin 60 | D4 — Data bus bit 4 |
| Pin 61 | D5 — Data bus bit 5 |
| Pin 62 | D6 — Data bus bit 6 |
| Pin 63 | D7 — Data bus bit 7 |
| Pin 64 | VCC — +5V power supply |
Typical Applications
MC68SEC000AE20 is suitable for 6 applications: Industrial Automation Controllers, Point-of-Sale (POS) Terminals, Medical Instrumentation Front-Ends, Automotive Body and Chassis ECUs, Legacy 16-bit Bus Peripheral Hubs, Educational Microprocessor Training Platforms.
Industrial Automation Controllers
The MC68SEC000AE20 fits industrial automation controllers because its 20 MHz M68K core delivers approximately 2 MIPS with deterministic 7-level vectored interrupts (6 internal + NMI), supporting responsive control loops on PLCs and CNC front-ends. Its TTL-compatible I/O interfaces directly with 5V industrial peripheral logic - optocouplers, 24V I/O transceivers, and legacy HMI displays - without level-shifters. The 24-bit address bus (16 MB linear) accommodates program Flash and parameter storage typical of machine controllers, while supervisor/user privilege modes support a protected real-time operating layer. Compared with newer ARM Cortex-M MCUs, the SEC000 brings M68K code reuse to factories that already run 68K firmware on existing equipment.
Recommended
Point-of-Sale (POS) Terminals
The MC68SEC000AE20 suits POS terminals where 32-bit M68K software compatibility, deterministic interrupt response, and low standby power are essential. The static CMOS design allows the clock to be halted during payment-card reader idle periods, dropping quiescent current dramatically and extending battery-backed UPS runtime. The 16-bit external data bus and 24-bit address bus handle graphic LCD framebuffers, thermal-printer buffers, and secure-key storage without external bus expansion. TTL-compatible I/O talks directly to legacy magnetic-stripe readers, keypads, and receipt printers common in retail equipment.
Recommended
Medical Instrumentation Front-Ends
The MC68SEC000AE20 is appropriate for medical instrumentation front-ends requiring deterministic 32-bit control and long product lifecycles. The static CMOS core supports clock gating between patient-sample acquisitions, lowering thermal dissipation in bedside enclosures where low surface temperature matters. Supervisor/user privilege modes allow isolated firmware regions for safety-critical routines, and the 7-level vectored interrupt structure handles prioritized tasks from analog front-ends, keypad input, and display updates. The 64-LQFP package enables reliable SMT assembly on medical-grade PCBs that must withstand autoclave or sterilization exposure in adjacent production lines.
Recommended
Automotive Body and Chassis ECUs
The MC68SEC000AE20 targets automotive body and chassis ECUs (door modules, climate control, instrument clusters) where M68K software compatibility, low quiescent draw during ignition-off, and 5V TTL I/O compatibility with legacy sensors are valued. The static core allows the clock to be stopped during vehicle parked state, dropping standby power so the ECU does not drain the 12V battery over weeks of inactivity. The 16-bit external bus and 24-bit address space handle body-controller firmware plus calibration tables, while the 7-level interrupt structure prioritizes CAN/LIN transceivers, sensor inputs, and actuator PWM. For new designs, an external watchdog supervisor and CAN transceiver are mandatory companions.
Recommended
Legacy 16-bit Bus Peripheral Hubs
The MC68SEC000AE20 serves as a hub controller in legacy 16-bit bus peripheral systems, including industrial I/O concentrators and data-acquisition front-ends that already use the M68K ISA. Its 16-bit external data bus matches the width of legacy peripheral ASICs, eliminating the need for bus-width translation glue logic. The 24-bit address bus supports direct mapping of peripheral register windows in a 16 MB address space without bank-switching. The 20 MHz clock sustains high-throughput DMA-style data movement, and the static design permits clock-frequency scaling for power-sensitive backplane applications.
Recommended
Educational Microprocessor Training Platforms
The MC68SEC000AE20 is widely used in university microprocessor training platforms because its M68K ISA, 16-bit external bus, and 7-level interrupt structure teach foundational concepts (supervisor/user modes, vectored autovectors, asynchronous bus cycles) that map cleanly onto later ColdFire and ARM designs. The static CMOS core allows instructors to single-step clock cycles on lab trainers, demonstrating pipeline and bus-arbitration behavior visually. The 64-LQFP package is breadboard-friendly via breakout PCBs, and the well-documented NXP datasheet simplifies lab exercises on assembly-language programming and memory interfacing. Course labs typically pair the part with SRAM, ROM/EPROM, and a 68540-style peripheral controller for complete system exploration.
Recommended
Recommended Products Summary
Engineering reference data for MC68SEC000AE20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68SEC000AE10 | MC68SEC000AE16 | MC68EC000AE20 | MC68HC000AE20 | MC68SEC000AE20 (Freescale) |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Freescale Semiconductor |
| Package | 64-LQFP (10x10) | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same |
| Maximum Clock Frequency | 20 MHz | 10 MHz | 16 MHz | 20 MHz | 20 MHz | 20 MHz |
| Core | EC000 static CMOS | EC000 static CMOS | EC000 static CMOS | EC000 non-static | HC000 non-static | EC000 static CMOS |
| Data Bus Width (external) | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit | 16-bit |
| Address Bus Width | 24-bit | 24-bit | 24-bit | 24-bit | 24-bit | 24-bit |
| Static Operation (clock-stop-at-DC) | Yes | Yes | Yes | No | No | Yes |
| Operating Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete (Rochester stock) |
Key Differentiators
- Fully-static CMOS with clock-stop-at-DC capability (vs MC68EC000AE20)
- Lowest-cost 32-bit MPU in NXP's M68K family (vs MC68HC000AE20)
- 20 MHz grade available for highest-throughput static designs (vs MC68SEC000AE16)
Design Notes
Estimated: at 20 MHz and 5V with all 16 data lines and 23 address lines switching on every bus cycle, the MC68SEC000AE20 typically draws 50-80 mA dynamic current. During static (clock-stopped) standby, current falls to single-digit mA for the CMOS core. To maximize standby savings, gate the CLK pin from a power-management controller and ensure RESET is properly sequenced before re-enabling the clock. Decouple VCC with 0.1uF ceramic + 10uF bulk placed within 5 mm of each VCC pin.
Route the asynchronous control signals (AS, UDS, LDS, DTACK, R/W, BR/BG/BGACK) with matched trace lengths to within 25 mm and avoid crossing the CLK trace. The E clock output is a free-running derivative of CLK - keep its trace short or series-terminate at 33 ohm to prevent overshoot on long backplane traces. Place the external SRAM/ROM and bus transceivers within 50 mm trace length to keep bus round-trip delays within the 4-clock asynchronous access budget.
Do not drive the FC0-FC2 pins to user-mode values during reset initialization; the MC68SEC000AE20 samples the function-code pins during reset to determine initial SSP and PC fetch address space, and an invalid combination can trap the CPU. Always pair the part with an external MAX705/MAX706-class voltage supervisor - the SEC000 has no internal POR for brownout below 4.5V. Confirm the HALT/RESET timing matches the datasheet's 100 ms reset-pulse minimum to avoid incomplete internal-state initialization.
Estimated: at 5V x 70 mA, the dynamic dissipation is approximately 350 mW; with theta_JA near 50 C/W for the 64-LQFP, the junction-to-ambient temperature rise is roughly 17.5 C. Thermal management is rarely a concern at full duty cycle, but designers should still provide a continuous ground plane under the part and avoid placing heat-generating passives within 5 mm of the package to keep junction temperature well below the 150 C maximum.
Compliance Information
Compliance status not present in the verified web data; set to 'unknown' per data authenticity rules. Part is obsolete per NXP product page.