LPC1317FBD64,551 - 72MHz Cortex-M3 MCU 64KB Flash | NXP
MPN: LPC1317FBD64,551 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.11 | $9.11 |
| 10 | $8.45 | $84.50 |
| 100 | $7.1 | $710.00 |
| 500 | $6.05 | $3,025.00 |
| 1,000 | $5.2 | $5,200.00 |
LPC1317FBD64,551 Overview
A microcontroller (MCU) is a single-chip computer that integrates a CPU core, program and data memory, and a wide range of peripherals such as timers, communication interfaces, ADC/DAC blocks, and GPIO. MCUs sit at the heart of nearly every embedded system, from industrial sensor nodes to consumer appliances, forming the lowest tier of the compute hierarchy alongside microprocessors, DSPs, and SoCs.
Key features of the LPC1317FBD64,551 include a 3-stage pipelined Cortex-M3 core with Harvard architecture (separate instruction/data buses plus a peripheral bus), USB device support, multiple USART ports, on-chip EEPROM, and the NXP MCU peripheral family. The device targets entry-level 32-bit applications where deterministic real-time behaviour, code density, and ease of use via the Cortex Microcontroller Software Interface Standard (CMSIS) are required.
The 72 MHz Cortex-M3 core provides 1.25 DMIPS/MHz (Dhrystone 2.1) performance, which is ample for protocol stacks, motor-control inner loops, and human-machine interface logic. The Harvard bus structure enables simultaneous fetches on the instruction and data paths, reducing stalls. Integrated EEPROM provides byte-erasable non-volatile storage for configuration or calibration records without external parts.
Typical applications include USB HID peripherals, industrial sensors, low-cost consumer devices, building automation, USB-to-UART bridges, and small motor-control subsystems. The combination of USB device plus USART plus GPIO makes it well suited as a flexible communications co-processor on larger boards.
When designing with the LPC1317FBD64,551, decouple VDD/VDDA with 100 nF ceramic capacitors placed close to each pin pair, and route the analog supply through a ferrite bead if the ADC is used. Confirm that the chosen crystal or internal oscillator setting matches the USB baud derivation tree when USB device operation is required.
This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes that complement the NXP datasheet and standard distributor listings.
Drop-in alternatives for LPC1317FBD64,551 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LPC1347FBD64,551
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LPC1315FBD64,551
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LPC1313FBD64,551
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LPC1343FBD64,551
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LPC1317FBD64,551 Maximum Ratings & Electrical Characteristics
| Core | ARM Cortex-M3 |
| Data Bus Width | 32 bit |
| Maximum Clock Frequency | 72 MHz |
| Program Memory Size | 64 KB (64K x 8) FLASH |
| RAM Size | 12 KB SRAM |
| EEPROM | On-chip |
| Package | 64-LQFP (10x10 mm) |
| Mounting Type | Surface Mount |
| USB | USB Device |
| USART | Yes (multiple instances) |
| RoHS Status | Compliant |
| CPU Architecture | Harvard, 3-stage pipeline |
LPC1317FBD64,551 Pin Configuration
| Pin 1 | P1_0 — GPIO / Wake-up |
| Pin 2 | P1_1 — GPIO |
| Pin 3 | P1_2 — GPIO |
| Pin 4 | P1_3 — GPIO |
| Pin 5 | P1_4 — GPIO |
| Pin 6 | P1_5 — GPIO |
| Pin 7 | P1_6 — GPIO |
| Pin 8 | P1_7 — GPIO |
| Pin 9 | P1_8 — GPIO |
| Pin 10 | P1_9 — GPIO |
| Pin 11 | VDD — Power supply |
| Pin 12 | VSS — Ground |
| Pin 13 | XTAL1 — Crystal oscillator input |
| Pin 14 | XTAL2 — Crystal oscillator output |
| Pin 15 | RST — Reset (active low) |
| Pin 16 | P2_0 — GPIO |
| Pin 17 | P2_1 — GPIO |
| Pin 18 | P2_2 — GPIO |
| Pin 19 | P2_3 — GPIO |
| Pin 20 | P2_4 — GPIO |
| Pin 21 | P2_5 — GPIO |
| Pin 22 | P2_6 — GPIO |
| Pin 23 | P2_7 — GPIO |
| Pin 24 | P2_8 — GPIO |
| Pin 25 | P2_9 — GPIO |
| Pin 26 | P2_10 — GPIO |
| Pin 27 | P2_11 — GPIO |
| Pin 28 | P2_12 — GPIO |
| Pin 29 | P2_13 — GPIO |
| Pin 30 | VDD — Power supply |
| Pin 31 | VSS — Ground |
| Pin 32 | P3_0 — GPIO |
| Pin 33 | P3_1 — GPIO |
| Pin 34 | P3_2 — GPIO / INT0 |
| Pin 35 | P3_3 — GPIO / INT1 |
| Pin 36 | P3_4 — GPIO |
| Pin 37 | P3_5 — GPIO |
| Pin 38 | P3_6 — GPIO |
| Pin 39 | P3_7 — GPIO |
| Pin 40 | P3_8 — GPIO |
| Pin 41 | P3_9 — GPIO |
| Pin 42 | P3_10 — GPIO |
| Pin 43 | P3_11 — GPIO |
| Pin 44 | P3_12 — GPIO |
| Pin 45 | P3_13 — GPIO |
| Pin 46 | P3_14 — GPIO |
| Pin 47 | VSS — Ground |
| Pin 48 | VDD — Power supply |
| Pin 49 | P0_0 — GPIO / ADC0 |
| Pin 50 | P0_1 — GPIO / ADC1 |
| Pin 51 | P0_2 — GPIO / ADC2 |
| Pin 52 | P0_3 — GPIO / ADC3 |
| Pin 53 | P0_4 — GPIO / ADC4 / SDA |
| Pin 54 | P0_5 — GPIO / ADC5 / SCL |
| Pin 55 | P0_6 — GPIO |
| Pin 56 | P0_7 — GPIO |
| Pin 57 | P0_8 — GPIO / USB_VBUS |
| Pin 58 | P0_9 — GPIO / USB_CONNECT |
| Pin 59 | P0_10 — GPIO / USB_DM |
| Pin 60 | P0_11 — GPIO / USB_DP |
| Pin 61 | P0_12 — GPIO |
| Pin 62 | P0_13 — GPIO |
| Pin 63 | P1_10 — GPIO |
| Pin 64 | P1_11 — GPIO |
Typical Applications
LPC1317FBD64,551 is suitable for 7 applications: USB HID Peripheral Devices, Industrial Sensor Nodes, Building Automation Controllers, USB-to-UART Bridge Modules, Small Motor Control Subsystems, Low-Cost Consumer Devices, Communication Co-Processor.
USB HID Peripheral Devices
The LPC1317FBD64,551 fits USB HID peripherals because its on-chip USB 2.0 full-speed Device controller, 72 MHz Cortex-M3 core, and 64 KB flash cover the firmware size and protocol stack needs of typical HID keyboards, mice, game controllers, and custom-interface devices. The 1.25 DMIPS/MHz headroom handles HID report parsing and debouncing without bottlenecks. Placed as the sole MCU with a USB connector and a 12 MHz crystal, the part also benefits from the on-chip USB bootloader that simplifies field firmware updates without an external programmer.
Recommended
Industrial Sensor Nodes
The LPC1317FBD64,551 suits industrial sensor nodes because its 64 KB flash accommodates protocol stacks such as Modbus RTU, the 12 KB SRAM buffers measurement bursts, and the multiple USARTs enable simultaneous RS-485 and debug-port connections. The 72 MHz Cortex-M3 core handles periodic sampling at sub-millisecond rates while remaining within the industrial temperature range documented for the LPC13xx family. Place the MCU alongside an isolated RS-485 transceiver and a 4-20 mA sensor front-end; the on-chip EEPROM stores calibration coefficients without external parts.
Recommended
Building Automation Controllers
The LPC1317FBD64,551 fits building automation controllers because its GPIO count, 64 KB flash, and USART peripherals support HVAC damper control, lighting keypads, and occupancy sensor hubs. The Cortex-M3 deterministic interrupt latency makes it suitable for time-sensitive control loops, while the on-chip EEPROM stores user configuration across power cycles. Pair with an isolated 24V-to-3.3V DC-DC and a triac driver stage; the MCU's GPIO slew rate is sufficient for direct low-side MOSFET drive at modest currents.
Recommended
USB-to-UART Bridge Modules
The LPC1317FBD64,551 is well matched to USB-to-UART bridge modules because the USB Device controller plus multiple USARTs implement CDC-ACM bridges with no external PHY required. The 64 KB flash fits composite USB-CDC plus vendor-class firmware, and the 72 MHz core keeps UART throughput comfortably below the USB full-speed limit. A minimal BOM uses just the MCU, a 12 MHz crystal, and an ESD-protected USB connector; firmware from NXP USB CDC reference stacks accelerates time-to-market.
Recommended
Small Motor Control Subsystems
The LPC1317FBD64,551 suits small brushed-DC and stepper motor subsystems because the Cortex-M3 72 MHz core runs trapezoidal commutation and basic PID loops with deterministic timing, while the GPIO and PWM timers drive H-bridge MOSFETs. The 64 KB flash fits state-machine plus speed-profile firmware, and the on-chip EEPROM holds calibrated current limits. Place the MCU adjacent to the gate driver; the GPIO slew rate is appropriate for logic-level MOSFETs at switching frequencies up to ~30 kHz.
Recommended
Low-Cost Consumer Devices
The LPC1317FBD64,551 fits low-cost consumer devices such as remote controls, smart-home sensor hubs, and appliance user-interface boards because the integrated peripherals (USB, USART, GPIO, timers, ADC) eliminate external components and reduce BOM cost. The 64 KB flash covers connectivity stacks and application logic, while the Cortex-M3 core keeps responsiveness snappy under interrupt-driven user input. Combine with a low-dropout regulator and a small OLED or LED indicator; the MCU's GPIO directly drives common-chars displays at modest frame frequencies.
Recommended
Communication Co-Processor
The LPC1317FBD64,551 works well as a communication co-processor on larger boards because its USB device, USARTs, and Cortex-M3 throughput offload protocol stacks from a host application processor. The 64 KB flash accommodates lightweight TCP/IP or proprietary RF-link glue code, and the GPIO can wake a host on incoming traffic. Place it adjacent to the host SoC with a UART or USB link; the on-chip EEPROM stores link credentials without an external memory part.
Recommended
Recommended Products Summary
Engineering reference data for LPC1317FBD64,551 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LPC1347FBD64,551 | LPC1315FBD64,551 | LPC1313FBD64,551 | LPC1343FBD64,551 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 64-LQFP (10x10) | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same |
| Core | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 |
| Maximum Clock Frequency | 72 MHz | 72 MHz | 72 MHz | 72 MHz | 72 MHz |
| Flash Size | 64 KB | 64 KB | 32 KB | 24 KB | 32 KB |
| SRAM Size | 12 KB | 12 KB | 8 KB | 8 KB | 8 KB |
| USB | USB 2.0 Full-Speed Device | USB 2.0 FS Device + bootloader | USB 2.0 FS Device | USB 2.0 FS Device | USB 2.0 FS Device |
| EEPROM | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) |
Key Differentiators
- Largest flash in LPC1317 64-LQFP family (vs LPC1315FBD64,551)
- Integrated USB 2.0 full-speed Device controller (vs LPC1313FBD64,551)
- On-chip EEPROM for parameter storage (vs Generic Cortex-M0 64-LQFP MCU)
Design Notes
Estimated: Decouple each VDD pin with a 100 nF X7R ceramic placed within 3 mm of the pin, and add a bulk 4.7 uF tantalum or ceramic near the package. The LPC1317FBD64,551 operates from a single 3.3 V supply rail; verify the absolute maximum VDD from the datasheet before applying 5 V to any GPIO. Sequence the analog and digital rails together if ADC accuracy matters.
Keep the 12 MHz crystal traces short and symmetric, with a guard ground pour to reduce EMI injection into the USB DP/DM pair. Route USB differential lines with 90 ohm differential impedance and place the ESD protection array close to the connector. Place the MCU's VSS pin via directly under the exposed pad (LQFP-64 does not have an exposed pad; use multiple through-vias to inner ground planes).
Do not enable the USB peripheral until the PLL is locked and the 48 MHz USB clock is stable, otherwise the host will enumerate failures. Confirm that the ISP entry pins are not pulled low at reset if you want the user application to run immediately. Verify unused GPIO are configured as outputs or inputs with the internal pull-up enabled to avoid floating-pin current draw.
Compliance Information
RoHS and REACH compliance per NXP product page. Not AEC-Q100 qualified - this part targets industrial and consumer applications.