P1013NSE2MHB - QorIQ P1 e500v2 1.055GHz SoC 689-TEPBGA | NXP
MPN: P1013NSE2MHB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $142.5 | $142.50 |
| 10 | $128.25 | $1,282.50 |
| 100 | $115 | $11,500.00 |
| 500 | $105.5 | $52,750.00 |
| 1,000 | $98.75 | $98,750.00 |
P1013NSE2MHB Overview
A microprocessor MPU (Microprocessor Unit) is the central processing element of an embedded computing system. Unlike a microcontroller MCU, an MPU typically lacks on-chip flash and relies on external DDR memory for program and data storage. The P1013NSE2MHB belongs to the QorIQ P1 communications processor family, positioned between simple MCUs and full multicore application processors. It is classified within the taxonomy: SoC -> MPU -> Power Architecture -> communications processor -> NXP QorIQ P1.
Key features of the P1013NSE2MHB include hardware-accelerated SEC for IPsec and SSL/TLS offload (saving CPU cycles for control-plane tasks), a DDR2/DDR3 memory controller with ECC for high-availability systems, three 10/100/1000 Ethernet MACs with integrated PHYs or SerDes interfaces, multiple PCIe Gen1 lanes, USB 2.0 host/device, and an integrated LCD controller for HMI panels. The die revision (Rev 2) provides silicon errata fixes relative to Rev 1.
Architecturally the P1013NSE2MHB pairs the e500v2 superscalar core with a high-bandwidth system bus interconnect to peripherals, a DPAA-lite style acceleration fabric, and dedicated engine blocks (SEC, PME). The advanced power-management features support dynamic frequency scaling and deep sleep modes, enabling fanless operation in thermally constrained networking appliances.
Typical applications include industrial gateway routers, smart-grid substation controllers, factory automation PLCs, HMI panels, single-board computers for IP-PBX and Unified Threat Management appliances, and networked industrial printers. The integrated GbE and SEC make it well suited for VPN and firewall line cards in SMB and branch-office networking equipment.
A core design consideration is the BGA package complexity - the 689-TEPBGA II (31x31 mm) requires multi-layer PCB with microvia or via-in-pad stackup, controlled-impedance routing for DDR3 and SerDes, and reflow oven with fine-pitch BGA capability; ensure a minimum 8-layer stackup with continuous ground planes under the BGA.
This page combines distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for P1013NSE2MHB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with P1013NSE2MHB (same form factor and footprint) — differing in Memory Controller, Ethernet, LCD Controller, Operating Temperature, USB.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
P1013NSE2HFB
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$58.9 / Unit
View Datasheet →P1013NSE2MFC
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
P1022NSE2MHB
✅ Drop-In✓ In Stock
$56.1 / Unit
View Datasheet →P1010NSE2HFB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
P1014NSE2HFB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
P1013NSE2MHB Maximum Ratings & Electrical Characteristics
| Architecture | Power Architecture e500v2 |
| Processor Series | QorIQ P1 (P1013) |
| Number of Cores | 1 |
| Maximum Core Frequency | 1.055 GHz |
| Instruction Set Width | 32-bit |
| Package | 689-TEPBGA II (31x31 mm) |
| Ethernet MACs | 3 x 10/100/1000 GbE |
| USB | USB 2.0 (host/device) |
| Memory Controller | DDR2/DDR3 with ECC |
| Security Engine | SEC (IPsec/SSL/TLS offload) |
| LCD Controller | Yes (integrated) |
| Operating Temperature | 0 C to 105 C |
| Mounting Type | Surface Mount (BGA) |
| Lead Free / RoHS | Lead Free / RoHS Compliant |
| Packaging | Tray |
| Silicon Revision | Rev 2 (Rev 1.1 per Mouser) |
P1013NSE2MHB 689-tepbga ii (31x31 mm) Pin Configuration Guide
Pin configuration for P1013NSE2MHB (689-tepbga ii (31x31 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for P1013NSE2MHB.
Refer to the datasheet for full pin configuration.
Typical Applications
P1013NSE2MHB is suitable for 6 applications: Industrial Gateway Routers, Smart-Grid Substation Controllers, Factory Automation PLCs, HMI Panels and Operator Interfaces, Networked Industrial Printers, IP-PBX and Unified Threat Management.
Industrial Gateway Routers
The P1013NSE2MHB's three integrated 10/100/1000 Ethernet MACs provide native multi-port routing without an external switch ASIC, while hardware-accelerated SEC offloads IPsec/SSL to free the e500v2 core for routing table processing. At 1.055 GHz the device sustains wire-speed NAT and firewall workloads typical of industrial protocol gateways (Modbus TCP, EtherNet/IP). The DDR2/DDR3 controller with ECC supports long-term memory reliability in 24/7 deployments, and the 0-105 C operating envelope tolerates factory-floor ambient. Located between the WAN uplink PHY and the internal LAN switch, the SoC replaces a discrete CPU plus three external MACs in a single 31x31 mm footprint.
Recommended
Smart-Grid Substation Controllers
The P1013NSE2MHB is well matched to IEC 61850 substation controllers: its ECC-protected DDR2/DDR3 controller detects single-bit memory faults critical to event-recording integrity, while the three GbE ports host process LAN, supervisory LAN, and protection interfaces without external bridges. The integrated LCD controller drives HMI panels at the substation front door, and SEC acceleration secures GOOSE/SV message authentication. Designers place the SoC alongside an IEC 61850-3 compliant PHY and small-form-factor DDR3 with ECC, accepting the 689-TEPBGA II thermal envelope under passive cooling. The 0-105 C operating temperature suits unheated outdoor cabinets in temperate climate zones.
Recommended
Factory Automation PLCs
In factory automation PLCs the P1013NSE2MHB executes real-time control loops and EtherNet/IP / PROFINET protocol stacks at 1.055 GHz, with the three GbE ports supporting deterministic industrial Ethernet plus a separate management interface. Hardware SEC offload encrypts OPC-UA traffic to the cloud without burdening the control loop, while the integrated LCD controller eliminates the need for a separate HMI ASIC. The DDR3 ECC memory detects single-bit SOFT errors that would otherwise violate IEC 61131-2 deterministic behavior. Mounted on a 8-layer control board, the SoC drives 24V-tolerant I/O backplanes and supports industrial -40 to +85 C extended ambient via the 0-105 C die junction envelope.
Recommended
HMI Panels and Operator Interfaces
The P1013NSE2MHB's integrated LCD controller drives TFT panels up to UXGA resolution, eliminating the external display bridge chip common in HMI designs. The e500v2 core runs Qt/Embedded or Web-based GUI stacks at 1.055 GHz with 3 GbE ports for controller-side, plant-side, and service-side networks. DDR3 with ECC prevents UI-state corruption from soft memory errors over long uptime cycles. The BGA package keeps the BOM small for panel-mount enclosures with depth constraints, and the industrial temperature envelope suits cabinet-mounted HMI installations in factory environments.
Recommended
Networked Industrial Printers
Industrial multi-function printers benefit from the P1013NSE2MHB's combination of three GbE ports (LAN, service, second-network), USB 2.0 for scanner modules, and SEC-accelerated IPsec for secure document transmission. At 1.055 GHz the SoC handles print-job rendering, panel UI, and network protocol stacks concurrently without saturating the e500v2 core. The LCD controller drives the operator panel natively, reducing BOM cost. DDR3 with ECC ensures print-job memory integrity across long duty cycles. This SoC is typically placed on the formatter board with rigid-flex PCB to the imaging and paper-transport subsystems.
Recommended
IP-PBX and Unified Threat Management
For SMB IP-PBX and unified threat-management (UTM) appliances the P1013NSE2MHB's hardware SEC engine offloads IPsec/SSL inspection, freeing the 1.055 GHz e500v2 core for VoIP signaling (SIP/H.323) and stateful firewall inspection. Three integrated GbE ports provide WAN, LAN, and DMZ segmentation without an external switch. DDR3 with ECC maintains call-record integrity in always-on deployments. The 689-TEPBGA II footprint fits 1U appliance form factors with bottom-mounted heatsink. The 0-105 C operating envelope supports typical closet-temperature deployments without active airflow, reducing BOM and MTBF risk.
Recommended
Recommended Products Summary
Engineering reference data for P1013NSE2MHB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | P1013NSE2HFB | P1013NSE2MFC | P1022NSE2MHB | P1010NSE2HFB | P1014NSE2HFB |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II (31x31 mm) | 689-TEPBGA II (31x31 mm) |
| Core Count | 1 x e500v2 | 1 x e500v2 | 1 x e500v2 | 2 x e500v2 | 1 x e500v2 | 1 x e500v2 |
| Core Frequency | 1.055 GHz | 1.055 GHz | 1.055 GHz | 1.055 GHz | 0.8 GHz (approx -25%) | 1.2 GHz (approx +14%) |
| GbE MACs | 3 | 3 | 3 | 3 | 3 | 3 |
| Memory Controller | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC | DDR2/DDR3 with ECC |
| Security Engine | SEC | SEC | SEC | SEC | SEC | SEC |
| Operating Temperature | 0 C to 105 C | 0 C to 105 C | 0 C to 105 C | 0 C to 105 C | 0 C to 105 C | 0 C to 105 C |
Key Differentiators
- Single-core e500v2 at 1.055 GHz in 689-TEPBGA II gives lowest-cost entry to QorIQ P1 communications SoCs (vs P1022NSE2MHB)
- Three integrated GbE MACs eliminate external switch ASIC in small-port gateways (vs P1010NSE2HFB)
- 1.055 GHz core bin balances throughput and power vs lower-priced 0.8 GHz P1010 (vs P1010NSE2HFB)
- Hard-coded 1.055 GHz bin matches most common gateway/CPE thermal and power budgets (vs P1014NSE2HFB)
Design Notes
The 689-TEPBGA II package (31x31 mm, 1.0 mm ball pitch) requires an 8-layer PCB minimum with microvia or via-in-pad stackup for signal breakout. Place a continuous ground plane immediately below the BGA to control impedance for DDR3 and SerDes traces. Per NXP P1013 hardware design guide, use 2 oz copper outer layers on 6-layer stackups to meet DDR3 SI requirements with reduced via stub impact. Thermal pads beneath the exposed die area must use an array of 0.3 mm thermal vias on a 1.0 mm pitch for heat dissipation.
DDR3 memory interfaces require 50-ohm single-ended and 100-ohm differential controlled-impedance routing, with all data lanes matched within 5 ps of byte-clock length and DQ-DQS within 25 ps of each byte group. Per the P1013 family reference design, route each SerDes lane on the top layer with reference ground and length-match within 0.15 mm. Keep the SEC and GbE lines isolated from noisy switching regulator zones, and avoid right-angle bends on any DDR3 or PCIe link.
Estimated: at typical workload, the P1013NSE2MHB dissipates approximately 4-7 W depending on GbE and SEC utilization. With theta-JA around 15 C/W for the 689-TEPBGA II package, junction rise is approximately 60-105 C above ambient. At 70 C cabinet ambient the die hits 130-175 C, which exceeds the 105 C spec; a passive heatsink or active airflow is mandatory, especially when DDR3 throughput saturates the memory controller and SEC engine together. [Input values: 5 W dissipation, 15 C/W theta-JA - confirm against your board layout.]
Do NOT boot the P1013NSE2MHB without configuring the Hard Reset Configuration Word (HRCW) and Boot Sequencer (BS) prior to power-on - the SoC will sample POR pins and attempt to boot from the wrong interface. Also ensure JTAG and BIST connections match the NXP development board reference schematics; mismatched TRST or HRESET pull-ups can lock out further debug access. When replacing P1013NSE2MHB with a P1014NSE2HFB or P1010NSE2HFB part, re-validate HRCW registers because frequency bin changes alter PowerPC PLL configuration. Always cross-check the latest errata document for the Rev 2 silicon on the NXP website before first prototype bring-up.
The P1013NSE2MHB requires multiple voltage rails (core, DDR3 I/O, SerDes, GbE I/O, USB, PLL) each with sequenced ramp-up per the datasheet. Place local 10 uF ceramic + 1 uF ceramic + 0.1 uF ceramic bypass at every rail, plus 100 uF bulk on the core rail. A 4-layer placement with dedicated power and ground planes is recommended. Estimated: total decoupling capacitance budget is approximately 600 uF across all rails when 1.055 GHz core is fully loaded; verify against the actual schematic with power-integrity simulation before final layout.
Compliance Information
RoHS compliant and lead-free per DigiChip parts listing and NXP product page. Reach, halogen-free status, and conflict-minerals compliance were not specified in the provided data and are listed as 'unknown'.
