PI7C9X111SLBFDE - PCIe-to-PCI Reversible Bridge | Diodes Inc
MPN: PI7C9X111SLBFDE ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.45 | $7,450.00 |
PI7C9X111SLBFDE Overview
A bridge IC (also called a PCI-to-PCI or PCIe-to-PCI bridge) is a protocol-translation device that connects two physically and electrically distinct bus segments. The PI7C9X111SL sits in the connectivity hierarchy as: bridge -> bus converter -> interface IC -> signal-conditioning semiconductor. It appears in systems that must glue a downstream legacy I/O controller (NIC, SCSI, industrial I/O, video capture) to an upstream host that no longer exposes a PCI bus, which is common after the industry migrated to PCIe-only chipsets around 2010-2015.
Key electrical and functional features include a single 3.3V supply rail, integrated PHY for PCIe Gen1 (2.5 GT/s) and PCI/PCI-X bus interface logic, support for both forward (PCIe primary, PCI secondary) and reverse (PCI primary, PCIe secondary) bridge modes, configurable via strapping pins, and 32-bit datapath operation up to 66 MHz. The 128-LQFP package exposes a generous pin budget so designers can route full 32-bit PCI plus x1 PCIe plus sideband control signals without an internal serializer.
The architecture is based on Diodes' (formerly Pericom) SlimLine PCIe-to-PCI bridge family, with on-chip transaction translation, posted write buffering, completion tracking, and standard PCI configuration space. Power consumption is optimized for embedded and add-in-card applications where a small footprint and low thermal dissipation are required. The part is qualified to operate over commercial temperature ranges suitable for embedded computing, networking, and industrial platforms.
Typical applications include PCIe-mini-PCI adapter cards, industrial PCs with legacy PCI I/O, embedded systems migrating from PCI to PCIe hosts, networking line cards that still require PCI peripheral controllers, test and instrumentation backplanes, and POS / kiosk / medical platforms with long-life PCI peripherals. The reversible bridge mode also supports evaluation boards and protocol-analyzer use cases where the host side of a PCI design needs to be exposed as a PCIe endpoint.
When designing with this device, pay close attention to the 3.3V rail decoupling (100 nF + 10 µF near the supply pins), PCIe AC-coupling capacitor placement on the transmit pair, and the strapping-pin configuration table for forward vs reverse mode selection. Reference clock routing and REFCLK+ / REFCLK- length matching must follow the PCIe CEM specification. Always verify the secondary PCI bus timing budget against the loaded PCI segment to avoid protocol violations at 66 MHz operation.
This page synthesizes distributor pricing, same-package drop-in alternatives, application companion chips, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for board bring-up, sourcing, and second-source planning.
Drop-in alternatives for PI7C9X111SLBFDE — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PI7C9X111SLBFDE (same form factor and footprint) — differing in PCIe Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PI7C9X111SLBFDEX
✅ Drop-In✓ In Stock
$5.5 / Unit
View Datasheet →PI7C9X111SL
✅ Drop-In📋 Reference alternative (not in catalog)
PI7C9X110BNBE
✅ Drop-In📋 Reference alternative (not in catalog)
PI7C9X110BBNBE
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
PX1011B-EL1
✅ Drop-In📋 Reference alternative (not in catalog)
PEX8112-AA13BI
✅ Drop-In📋 Reference alternative (not in catalog)
PI7C9X111SLBFDE Maximum Ratings & Electrical Characteristics
| Function | PCI Express to PCI Reversible Bridge |
| PCIe Interface | x1 Lane, Gen1 (2.5 GT/s) |
| PCI Interface | 32-bit, 33/66 MHz PCI; 66 MHz PCI-X |
| Bridge Mode | Forward and Reverse (configurable) |
| Supply Voltage | 3.3 V (single rail) |
| Package | 128-LQFP (14x14 mm) |
| Pin Count | 128 |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (TR) |
| ECCN | EAR99 |
| Introduction Date | June 10, 2008 |
| Part Status | Active |
PI7C9X111SLBFDE 128-lqfp (14x14 mm) Pin Configuration Guide
Pin configuration for PI7C9X111SLBFDE (128-lqfp (14x14 mm) package). This power device features gate, drain, and source terminals. For non-polarized packages, refer to the manufacturer datasheet for exact pin 1 orientation and footprint details. Common applications include power supply design, motor driving, and load switching.
No detailed pinout data available for PI7C9X111SLBFDE.
Refer to the datasheet for full pin configuration.
Typical Applications
PI7C9X111SLBFDE is suitable for 6 applications: PCIe to mini-PCI Adapter Card, Industrial PC with Legacy PCI I/O, Embedded System PCI to PCIe Migration, Networking Line Card with PCI Peripheral Controllers, Test & Instrumentation Backplane Bridge, Medical Imaging Platform PCI Bridge.
PCIe to mini-PCI Adapter Card
The PI7C9X111SLBFDE fits PCIe-to-mini-PCI adapter cards because it bridges a single x1 PCIe upstream lane to a 32-bit PCI downstream bus that matches the mini-PCI electrical profile. With integrated PCIe Gen1 PHY, the chip eliminates external transceivers, freeing board area for the mini-PCI socket and antenna connectors. Designers using the device in reverse mode can also expose mini-PCI peripherals behind a legacy PCI host in test setups. Add 100 nF + 10 µF decoupling on each 3.3V pin cluster, follow PCIe CEM routing on the upstream side, and length-match REFCLK+/REFCLK- to within 100 mils.
Recommended
Industrial PC with Legacy PCI I/O
The PI7C9X111SLBFDE supports industrial PCs that need to retain legacy 32-bit PCI I/O cards (data acquisition, frame grabbers, motion controllers) when the host chipset has migrated to PCIe-only. The 32-bit 33/66 MHz PCI bus interface preserves compatibility with long-life industrial peripherals, while the x1 PCIe upstream interface aligns with current-generation embedded CPUs. Single 3.3V supply operation simplifies the BOM, and the 128-LQFP package is well suited to the larger board area typical of industrial PCBs. Configure the bridge for forward mode via strapping pins and verify the loaded PCI bus timing budget at 66 MHz.
Recommended
Embedded System PCI to PCIe Migration
The PI7C9X111SLBFDE enables embedded systems to migrate from PCI-only hosts to PCIe-only hosts without rewriting peripheral firmware, by bridging a downstream PCI/PCI-X bus to an upstream PCIe Gen1 link. This is critical for medical imaging, POS, kiosk, and test-and-measurement platforms whose peripheral IP has 10-20 year lifecycles. The reversible bridge mode allows the same chip to be used as a host-side bridge during evaluation, exposing the PCIe endpoint downstream. Use posted-write buffering to mask the latency difference between 66 MHz PCI-X and x1 PCIe Gen1.
Recommended
Networking Line Card with PCI Peripheral Controllers
The PI7C9X111SLBFDE bridges PCIe line-card CPUs to PCI peripheral controllers (encryption offload, TDM, legacy fabric interfaces) that are still shipping as 32-bit PCI parts. Its single 3.3V supply and integrated PHY reduce BOM cost versus bridges requiring multiple rails, which matters in the cost-sensitive line-card market. The 128-LQFP package fits the standard line-card form factor, and the 66 MHz PCI-X mode supports faster offload engines. Place PCIe AC-coupling capacitors within 200 mils of the transmit pins and route REFCLK with controlled impedance.
Recommended
Test & Instrumentation Backplane Bridge
The PI7C9X111SLBFDE is well suited to test and instrumentation backplanes that must expose a PCIe test host to legacy PCI instruments, or vice versa using reverse mode. The reversible bridge capability allows a single FPGA-based test head to interface with either PCIe or PCI instrument cards via configuration cycles. The 32-bit datapath at 66 MHz supports streaming acquisition rates typical of oscilloscope and logic analyzer backplanes. Use the chip's posted-write buffering to absorb burst transfers from high-speed digitizers.
Recommended
Medical Imaging Platform PCI Bridge
The PI7C9X111SLBFDE bridges the PCIe host of medical imaging platforms (CT, ultrasound, X-ray controllers) to 32-bit PCI frame grabbers and DSP cards whose firmware lifecycles span regulatory certification cycles. The 3.3V-only supply simplifies the safety-isolated power tree typical of medical equipment. The 128-LQFP package is well known to medical design teams already comfortable with PCI bridge layouts. Forward bridge mode with 66 MHz PCI-X support handles the high data rates of modern image sensors without dropping frames.
Recommended
Recommended Products Summary
Engineering reference data for PI7C9X111SLBFDE — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PI7C9X111SLBFDEX | PI7C9X111SL | PI7C9X110BNBE | PI7C9X110BBNBE | PX1011B-EL1 | PEX8112-AA13BI |
|---|---|---|---|---|---|---|---|
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Microchip Technology | Broadcom |
| Package | 128-LQFP (14x14) | 128-LQFP (14x14) | 128-LQFP (14x14) | 128-LQFP (14x14) | 128-LQFP (14x14) | 128-LQFP (14x14) | 128-LQFP (14x14) |
| PCIe Interface | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) | x1 Gen1 (2.5 GT/s) |
| PCI Interface | 32-bit, 33/66 MHz, PCI-X | 32-bit, 33/66 MHz, PCI-X | 32-bit, 33/66 MHz, PCI-X | 32-bit, 33 MHz, no PCI-X | 32-bit, 33 MHz, no PCI-X | 32-bit, 33/66 MHz, PCI-X | 32-bit, 33/66 MHz, PCI-X |
| Bridge Mode | Reversible (forward + reverse) | Reversible | Reversible | Forward only | Forward only | Reversible | Reversible |
| Supply Voltage | 3.3 V single rail | 3.3 V single rail | 3.3 V single rail | 3.3 V single rail | 3.3 V single rail | 3.3 V single rail | 3.3 V single rail |
| Integrated PHY | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Reversible bridge mode in a single 128-LQFP package (vs PI7C9X110BNBE)
- 66 MHz PCI-X support for legacy high-performance peripherals (vs PI7C9X110BNBE)
- Single 3.3V supply operation simplifies the BOM (vs PEX8112-AA13BI (Broadcom))
Design Notes
The PI7C9X111SLBFDE operates from a single 3.3V supply rail. Place a 100 nF ceramic decoupling capacitor within 50 mils of every 3.3V power pin cluster, with a bulk 10 µF tantalum or ceramic capacitor near the supply entry. The integrated PCIe PHY draws transient current during PLL lock and link training, so additional bulk capacitance (22 µF) close to the chip improves link-up margin on noisy backplanes. Estimated: at x1 Gen1 link-up, peak current draw is roughly 250 mA; verify against the latest datasheet revision before finalizing the power tree.
Route the PCIe transmit pair (PETp0/PETn0) and receive pair (PERp0/PERn0) as a 90 Ω differential pair with 100 Ω AC-coupling capacitors on each transmit pin within 200 mils of the bridge. Match REFCLK+/REFCLK- lengths to within 100 mils and route them as a 100 Ω differential pair. The 128-LQFP pinout is dense, so use a 4-layer PCB with a dedicated ground plane beneath the LQFP to keep return paths continuous. Follow the PCI Bus ECN for 66 MHz PCI-X trace length matching on the 32-bit AD bus.
At 66 MHz PCI-X operation, the 32-bit AD bus generates significant SSO (Simultaneous Switching Output) noise on the 3.3V supply. Add 0.01 µF and 0.1 µF decoupling spread across the AD bus pins, not just at the supply pins. Keep the PCI-X clock trace length matched to the AD bus within 250 mils. For embedded designs near switching regulators, isolate the bridge's analog 3.3V rail using a ferrite bead or LDO to prevent power-supply noise from coupling into the PCI-X clock.
Do not forget to configure the strapping pins for forward vs reverse bridge mode at reset, or the chip will default to an undefined state and fail enumeration. Always include a 100 kΩ pull-up on PERST# and a 10 kΩ pull-up on SMBDAT to ensure I2C-style management interface works correctly. Avoid leaving NC (no-connect) pins floating if your PCB layout tool flags them - tie them to ground through 10 kΩ resistors to prevent ESD latch-up. Estimated: missed strapping pin configuration is the #1 cause of PI7C9X111SL link-up failures in lab bring-up.
Compliance Information
Compliance values for RoHS, REACH, lead-free, halogen-free, and conflict minerals are not present in the verified web data and are marked unknown rather than guessed. ECCN EAR99 is sourced from the GlobalSpec datasheet listing. AEC-Q100 is not applicable because this is an industrial/commercial bridge IC, not an automotive-qualified part.
