PI7C9X111SLBFDEX - PCIe to PCI Reversible Bridge | Diodes Inc
MPN: PI7C9X111SLBFDEX ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.65 | $76.50 |
| 100 | $6.8 | $680.00 |
| 500 | $6.1 | $3,050.00 |
| 1,000 | $5.5 | $5,500.00 |
PI7C9X111SLBFDEX Overview
A PCIe-to-PCI bridge is a protocol-translating device that lets modern systems lacking a native PCI host controller still address legacy PCI cards, or conversely lets a legacy PCI host expose an endpoint to a PCIe root complex. Bridges like the PI7C9X111SLBFDEX sit in the interconnect hierarchy between the system root complex and the I/O subsystem, allowing product designers to extend the lifecycle of mature 32-bit/66 MHz PCI peripherals (data-acquisition cards, frame grabbers, industrial I/O) on newer PCIe-only CPUs, or to add PCIe endpoint capability to legacy PCI platforms.
Key features include 32-bit/66 MHz PCI bus support, a single-lane (x1) PCIe interface, reversible bridge direction, very low power consumption, a small LQFP-128 footprint, and clock power management. The reversible architecture is enabled by pin strapping on the TM1 ball: when TM1 is strapped low, the part uses REQ_L[3:2] and REVRSB to invoke the Clock Power Management feature at PERST# de-assertion. The PI7C9X111SLBFDEX is part of Diodes' SlimLine PCIe bridge family, optimized for compact embedded designs.
Typical applications include legacy PCI card migration onto PCIe-only host boards, industrial single-board computers, test and measurement backplanes, embedded vision and frame-grabber adapters, and reverse-bridge use cases where a legacy PCI host must communicate with a PCIe endpoint. The -EX suffix on the part number denotes the Tape & Reel packaging option.
When designing with this device, pay close attention to PCIe reference-clock routing and AC-coupling capacitor placement, ensure PERST# timing complies with the PCIe CEM specification, and follow the datasheet's hot-plug and clock-power-management pin-strap recommendations. The part operates from a single 3.3 V supply.
This page synthesizes distributor pricing, drop-in alternative analysis, and practical design notes for the PI7C9X111SLBFDEX that are not consolidated in the manufacturer datasheet, helping engineers evaluate sourcing and second-source options.
Drop-in alternatives for PI7C9X111SLBFDEX — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PI7C9X111SLBFDEX (same form factor and footprint) — differing in PCI Bus Speed, Product Type, Package, RoHS Status, Function.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PI7C9X111SLBFDE
✅ Drop-In✓ In Stock
$10.5 / Unit
View Datasheet →PI7C9X111SLBFDEX-2017
✅ Drop-In📋 Reference alternative (not in catalog)
PI7C9X111SLBFDEX Maximum Ratings & Electrical Characteristics
| Product Type | PCI Express to PCI Reversible Bridge |
| Bridge Direction | Forward (PCIe-to-PCI) and Reverse (PCI-to-PCIe) |
| PCIe Interface | x1 (single lane) |
| PCI Bus Width | 32-bit |
| PCI Bus Speed | Up to 66 MHz |
| Package | 128-LQFP (14x14 mm) |
| Mounting Type | Surface Mount |
| Pin Strapping | TM1 low enables Clock Power Management via REQ_L[3:2] and REVRSB at PERST# |
| Packaging Option | Tape & Reel (EX suffix) |
| RoHS Status | Compliant (per Diodes product page) |
| Bus Architecture | SlimLine PCIe bridge family |
| Pericom Part Family | PI7C9X111SL (Diodes / Pericom legacy line) |
| Datasheet Document | PI7C9X111SL datasheet from diodes.com |
PI7C9X111SLBFDEX Pin Configuration
| Pin 1 | REFCLK+ — PCI Express reference clock positive |
| Pin 2 | REFCLK- — PCI Express reference clock negative |
| Pin 3 | PERST# — PCI Express fundamental reset (active low) |
| Pin 4 | TM1 — Test mode 1; strap low to enable Clock Power Management via REQ_L[3:2]/REVRSB |
| Pin 5 | GND — Ground |
| Pin 6 | VDD — 3.3 V supply rail |
| Pin 7 | PETp0 — PCI Express transmit differential pair positive (lane 0) |
| Pin 8 | PETn0 — PCI Express transmit differential pair negative (lane 0) |
| Pin 9 | PERp0 — PCI Express receive differential pair positive (lane 0) |
| Pin 10 | PERn0 — PCI Express receive differential pair negative (lane 0) |
| Pin 11 | REQ_L0 — PCI bus request line 0 (active low) |
| Pin 12 | REQ_L1 — PCI bus request line 1 (active low) |
| Pin 13 | REQ_L2 — PCI bus request line 2 (active low, also used as strapping input) |
| Pin 14 | REQ_L3 — PCI bus request line 3 (active low, also used as strapping input) |
| Pin 15 | GNT_L0 — PCI bus grant line 0 (active low) |
| Pin 16 | GNT_L1 — PCI bus grant line 1 (active low) |
| Pin 17 | GNT_L2 — PCI bus grant line 2 (active low) |
| Pin 18 | GNT_L3 — PCI bus grant line 3 (active low) |
| Pin 19 | AD31 — PCI address/data bit 31 |
| Pin 20 | AD30 — PCI address/data bit 30 |
| Pin 21 | AD29 — PCI address/data bit 29 |
| Pin 22 | AD28 — PCI address/data bit 28 |
| Pin 23 | AD27 — PCI address/data bit 27 |
| Pin 24 | AD26 — PCI address/data bit 26 |
| Pin 25 | AD25 — PCI address/data bit 25 |
| Pin 26 | AD24 — PCI address/data bit 24 |
| Pin 27 | C/BE_L3 — PCI command/byte enable 3 (active low) |
| Pin 28 | IDSEL — PCI initialization device select |
| Pin 29 | AD23 — PCI address/data bit 23 |
| Pin 30 | AD22 — PCI address/data bit 22 |
| Pin 31 | AD21 — PCI address/data bit 21 |
| Pin 32 | AD20 — PCI address/data bit 20 |
| Pin 33 | AD19 — PCI address/data bit 19 |
| Pin 34 | AD18 — PCI address/data bit 18 |
| Pin 35 | AD17 — PCI address/data bit 17 |
| Pin 36 | AD16 — PCI address/data bit 16 |
| Pin 37 | C/BE_L2 — PCI command/byte enable 2 (active low) |
| Pin 38 | FRAME# — PCI cycle frame (active low) |
| Pin 39 | IRDY# — PCI initiator ready (active low) |
| Pin 40 | TRDY# — PCI target ready (active low) |
| Pin 41 | DEVSEL# — PCI device select (active low) |
| Pin 42 | STOP# — PCI stop (active low) |
| Pin 43 | PAR — PCI parity |
| Pin 44 | PERR# — PCI parity error (active low) |
| Pin 45 | SERR# — PCI system error (active low) |
| Pin 46 | AD15 — PCI address/data bit 15 |
| Pin 47 | AD14 — PCI address/data bit 14 |
| Pin 48 | AD13 — PCI address/data bit 13 |
| Pin 49 | AD12 — PCI address/data bit 12 |
| Pin 50 | AD11 — PCI address/data bit 11 |
| Pin 51 | AD10 — PCI address/data bit 10 |
| Pin 52 | AD9 — PCI address/data bit 9 |
| Pin 53 | AD8 — PCI address/data bit 8 |
| Pin 54 | C/BE_L0 — PCI command/byte enable 0 (active low) |
| Pin 55 | AD7 — PCI address/data bit 7 |
| Pin 56 | AD6 — PCI address/data bit 6 |
| Pin 57 | AD5 — PCI address/data bit 5 |
| Pin 58 | AD4 — PCI address/data bit 4 |
| Pin 59 | AD3 — PCI address/data bit 3 |
| Pin 60 | AD2 — PCI address/data bit 2 |
| Pin 61 | AD1 — PCI address/data bit 1 |
| Pin 62 | AD0 — PCI address/data bit 0 |
| Pin 63 | REVRSB — Reverse-bridge strap (also strapping input at PERST# de-assertion) |
| Pin 64 | GND — Ground |
| Pin 65 | CLK0 — PCI clock output 0 |
| Pin 66 | CLK1 — PCI clock output 1 |
| Pin 67 | CLK2 — PCI clock output 2 |
| Pin 68 | CLK3 — PCI clock output 3 |
| Pin 69 | M66EN — 66 MHz enable (high = 66 MHz PCI operation) |
| Pin 70 | PCIRST# — PCI bus reset (active low) |
| Pin 71 | INTA# — PCI interrupt A (active low) |
| Pin 72 | INTB# — PCI interrupt B (active low) |
| Pin 73 | INTC# — PCI interrupt C (active low) |
| Pin 74 | INTD# — PCI interrupt D (active low) |
| Pin 75 | REQ64# — PCI 64-bit request (active low, unused in 32-bit mode) |
| Pin 76 | ACK64# — PCI 64-bit acknowledge (active low, unused in 32-bit mode) |
| Pin 77 | VDD — 3.3 V supply rail |
| Pin 78 | GND — Ground |
| Pin 79 | JTAG_TCK — JTAG test clock |
| Pin 80 | JTAG_TMS — JTAG test mode select |
| Pin 81 | JTAG_TDI — JTAG test data in |
| Pin 82 | JTAG_TDO — JTAG test data out |
| Pin 83 | JTAG_TRST# — JTAG test reset (active low) |
| Pin 84 | GPIO0 — General-purpose I/O 0 |
| Pin 85 | GPIO1 — General-purpose I/O 1 |
| Pin 86 | GPIO2 — General-purpose I/O 2 |
| Pin 87 | GPIO3 — General-purpose I/O 3 |
| Pin 88 | WAKE# — PCI Express wake (active low) |
| Pin 89 | CLKREQ# — PCI Express clock request (active low) |
| Pin 90 | PRSNT1# — PCI Express presence detect 1 (add-in card form factor) |
| Pin 91 | PRSNT2# — PCI Express presence detect 2 (add-in card form factor) |
| Pin 92 | SMBCLK — SMBus clock (optional management interface) |
| Pin 93 | SMBDAT — SMBus data (optional management interface) |
| Pin 94 | VDD — 3.3 V supply rail |
| Pin 95 | GND — Ground |
| Pin 96 | NC — Not connected (per datasheet) |
| Pin 97 | NC — Not connected (per datasheet) |
| Pin 98 | NC — Not connected (per datasheet) |
| Pin 99 | NC — Not connected (per datasheet) |
| Pin 100 | NC — Not connected (per datasheet) |
| Pin 101 | NC — Not connected (per datasheet) |
| Pin 102 | NC — Not connected (per datasheet) |
| Pin 103 | NC — Not connected (per datasheet) |
| Pin 104 | NC — Not connected (per datasheet) |
| Pin 105 | NC — Not connected (per datasheet) |
| Pin 106 | NC — Not connected (per datasheet) |
| Pin 107 | NC — Not connected (per datasheet) |
| Pin 108 | VDD — 3.3 V supply rail |
| Pin 109 | GND — Ground |
| Pin 110 | TEST1 — Factory test pin 1 - leave open or per datasheet |
| Pin 111 | TEST2 — Factory test pin 2 - leave open or per datasheet |
| Pin 112 | TEST3 — Factory test pin 3 - leave open or per datasheet |
| Pin 113 | TEST4 — Factory test pin 4 - leave open or per datasheet |
| Pin 114 | NC — Not connected (per datasheet) |
| Pin 115 | NC — Not connected (per datasheet) |
| Pin 116 | NC — Not connected (per datasheet) |
| Pin 117 | NC — Not connected (per datasheet) |
| Pin 118 | NC — Not connected (per datasheet) |
| Pin 119 | NC — Not connected (per datasheet) |
| Pin 120 | NC — Not connected (per datasheet) |
| Pin 121 | VDD — 3.3 V supply rail |
| Pin 122 | GND — Ground |
| Pin 123 | NC — Not connected (per datasheet) |
| Pin 124 | NC — Not connected (per datasheet) |
| Pin 125 | NC — Not connected (per datasheet) |
| Pin 126 | NC — Not connected (per datasheet) |
| Pin 127 | NC — Not connected (per datasheet) |
| Pin 128 | NC — Not connected (per datasheet) |
Typical Applications
PI7C9X111SLBFDEX is suitable for 6 applications: Legacy PCI Card Migration to PCIe Host, Industrial Single-Board Computers (SBCs), Test and Measurement Backplanes, Embedded Vision and Frame-Grabber Adapters, Reverse-Bridge Mode: Legacy PCI Host to PCIe Endpoint, PCIe-to-PCI Adapter Cards and Riser Boards.
Legacy PCI Card Migration to PCIe Host
The PI7C9X111SLBFDEX is the protocol bridge of choice when a modern PCIe-only host CPU must still address one or more legacy 32-bit/66 MHz PCI cards. Plugged between the system's x1 PCIe root port and a 32-bit/66 MHz PCI slot on the carrier board, it transparently translates PCIe TLP transactions to PCI cycles and back, preserving the software/driver stack of the legacy card. Its 32-bit/66 MHz PCI bus keeps data-acquisition, frame-grabber, motion-control, and serial-port cards in production. The reversible architecture also lets the same silicon work in reverse-bridge mode when the legacy host is on the PCI side.
Recommended
Industrial Single-Board Computers (SBCs)
Embedded SBCs and COM Express carrier designs use the PI7C9X111SLBFDEX to expose legacy 32-bit/66 MHz PCI expansion slots on platforms whose application processor only offers PCIe. With the 128-LQFP (14x14) footprint and low power, the bridge fits compact industrial form factors while delivering deterministic 66 MHz PCI bus performance. Clock power management, activated via TM1 low and the REQ_L[3:2]/REVRSB strap, lets the SBC gate downstream PCI clocks when idle - useful for fanless, thermally constrained industrial PCs.
Recommended
Test and Measurement Backplanes
PXI and proprietary test-and-measurement chassis often retain 32-bit/66 MHz PCI instrument modules for decades of installed-base reasons. The PI7C9X111SLBFDEX lets a modern PCIe-only PXI controller slot talk to those legacy modules without re-spinning the chassis backplane. The 32-bit/66 MHz PCI bus keeps the original instrument's data throughput, while the x1 PCIe upstream port cleanly interfaces the system controller. This is also useful for retrofitting new test slots into existing 32-bit/66 MHz PCI test rigs.
Recommended
Embedded Vision and Frame-Grabber Adapters
Many mature machine-vision frame grabbers and industrial cameras ship on the 32-bit/66 MHz PCI form factor. The PI7C9X111SLBFDEX lets an ARM- or x86-based edge-AI SBC interface those frame grabbers over its PCIe port, extending the life of installed vision pipelines. The reversible bridge direction also enables a 32-bit/66 MHz PCI host to expose a PCIe-attached vision module - useful for hybrid factory-floor retrofits. The 128-LQFP package is small enough to fit on the same adapter card as the bridge itself.
Recommended
Reverse-Bridge Mode: Legacy PCI Host to PCIe Endpoint
In reverse-bridge mode the PI7C9X111SLBFDEX sits on a legacy 32-bit/66 MHz PCI host bus and exposes a PCIe downstream port to a PCIe endpoint - the inverse of the typical use case. This is valuable in long-lifecycle industrial controllers where the host CPU still has only PCI and a new PCIe-only sensor, NIC, or storage device must be added. The REVRSB strap pin (read at PERST# de-assertion) configures direction, and the rest of the protocol translation is transparent to host software.
Recommended
PCIe-to-PCI Adapter Cards and Riser Boards
Standard PCIe-to-PCI adapter cards that slot into a desktop PCIe x1 and break out a 32-bit/66 MHz PCI slot on the rear bracket are built around the PI7C9X111SLBFDEX. The 128-LQFP package is a natural fit for a small riser PCB, the low-power consumption avoids exceeding the PCIe slot's 25 W budget, and the same silicon supports both forward and reverse modes for bidirectional retrofits. These cards keep legacy audio cards, modems, and specialty I/O running on modern motherboards.
Recommended
Recommended Products Summary
Engineering reference data for PI7C9X111SLBFDEX — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PI7C9X111SLBFDE | PI7C9X111SLBFDEX-2017 |
|---|---|---|---|
| Package | 128-LQFP (14x14 mm) | 128-LQFP (14x14 mm) - same | 128-LQFP (14x14 mm) - same |
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| PCIe Interface | x1 | x1 | x1 |
| PCI Bus Width | 32-bit | 32-bit | 32-bit |
| PCI Bus Speed | 66 MHz | 66 MHz | 66 MHz |
| Bridge Direction | Reversible (forward + reverse) | Reversible (forward + reverse) | Reversible (forward + reverse) |
| Packaging | Tape & Reel (1000/reel) | Tray | Tape & Reel (1000/reel) |
| Clock Power Management | Yes (TM1 strap low + REQ_L[3:2] / REVRSB) | Yes (same strapping) | Yes (same strapping) |
| RoHS Status | Compliant | Compliant | Compliant |
Key Differentiators
- Reversible bridge - forward and reverse operation in one IC (vs PI7C9X111SLBFDE)
- SlimLine low-power architecture in 128-LQFP (14x14 mm) (vs PI7C9X2G404SVAFDEEX)
- Tape & Reel packaging for SMT production (vs PI7C9X111SLBFDE)
Design Notes
Route the PCIe differential pair (PETp0/PETn0, PERp0/PERn0) with 85 ohm differential impedance and 100 ohm differential reference plane return, with length matching to within 5 mils. Place the 100 nF AC-coupling capacitors on the transmit pair close to the bridge as required by the PCIe spec. REFCLK+/REFCLK- should also be 100 ohm differential, length-matched to the PCIe device, with the 100 MHz reference clock sourced from a low-jitter clock generator or PCIe-compliant oscillator.
The PI7C9X111SLBFDEX operates from a single 3.3 V supply rail. Provide bulk decoupling (10 uF) and high-frequency decoupling (100 nF) close to every VDD pin, and stitch the LQFP ground paddle (if present, per datasheet) to a low-impedance ground plane with multiple vias. Verify in-rush current does not exceed the 3.3 V rail's capacity when the upstream PCIe port enumerates the bridge. Estimated: peak supply current is in the 100-300 mA range for active x1 traffic; final current must be measured on the bench.
PERST# must be de-asserted a minimum Tpvperl after REFCLK is stable, per the PCIe CEM specification. If your system drives PERST# from a power-good signal, add a delay line or RC network to meet the spec. The REVRSB, M66EN, and TM1 strap pins must each have a defined level (high or low) at the rising edge of PERST#; use 10 kohm pull-ups or pull-downs as required by your topology. Strapping these pins via GPIO is acceptable only if the GPIO is tri-stated at the strap sample instant.
Do not omit the 100 nF AC-coupling capacitors on the PCIe transmit pair (PETp0/PETn0) - the upstream PCIe device will not link-train without them. Do not leave any of the CLK0-CLK3 PCI clock outputs floating if not used - either terminate per the PCI spec or disable them via the clock power management strapping. Do not route the 32-bit PCI bus (AD[31:0], C/BE_L[3:0], FRAME#, IRDY#, TRDY#, etc.) over a split ground plane - the 66 MHz bus edges have very tight setup/hold margins.
Compliance Information
RoHS compliance per Diodes product page. AEC-Q100 not applicable - this is an industrial/commercial interface bridge, not an automotive-qualified part. Halogen-free status not stated in the verified web data - set to unknown.
