SI5330B-B00206-GMR - 1:4 LVDS Clock Buffer/Translator | Skyworks
MPN: SI5330B-B00206-GMR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.92 | $3.92 |
| 10 | $3.53 | $35.30 |
| 100 | $2.95 | $295.00 |
| 500 | $2.62 | $1,310.00 |
| 1,000 | $2.4 | $2,400.00 |
| 3,000 | $2.15 | $6,450.00 |
SI5330B-B00206-GMR Overview
A clock buffer (also called a clock fanout buffer or clock translator) is a specialized timing IC that takes one incoming reference clock and replicates it across multiple low-skew outputs, optionally shifting voltage standards along the way. Clock buffers sit in the timing tree between a primary PLL/oscillator and downstream devices such as ADCs, DACs, FPGAs, ASICs, and SERDES PHYs. Modern clock buffers like the Si5330 family are evaluated less by raw frequency and more by additive phase jitter, output-to-output skew, and PSRR-equivalent supply noise immunity; the Si5330 series targets the sub-1 ps RMS additive jitter class typical of 1 Gb to 10 Gb serial-link reference clocks.
Key features of the SI5330B-B00206-GMR include: 1:4 fanout from a single reference; support for differential-input signaling (LVDS, LVPECL, HCSL, CML) and single-ended CMOS/SSTL/HSTL; configurable output format and voltage; built-in level translation between input and output standards; very low output-to-output skew (typically tens of picoseconds); and a wide 1 MHz to 710 MHz output frequency range. The exposed thermal pad (EP) of the QFN-24 package provides a low-theta-JA path to PCB copper for high-temperature operation.
Architecturally, the Si5330 uses a differential input receiver followed by a low-jitter PLL/buffer core and four matched output drivers; the B-order code (B00206) selects the LVDS-specific output configuration, with internal source-termination and bias networks that eliminate most external component requirements and reduce BOM count versus discrete solutions.
Typical applications include: clock distribution for multi-lane SERDES in networking switches and routers; fanout for FPGA/ASIC reference clocks; ADC/DAC sampling-clock distribution in test and measurement; redundant clock switching in telecom line cards; and low-jitter timing for video broadcasting and broadcast-grade audio sample-rate converters. Designers often pair the Si5330 with a primary oscillator or PLL such as the Si5351/Si5341 family upstream and an FPGA downstream.
Designers should pay attention to the exposed pad layout - it must be soldered to a sufficiently large copper pour to meet the theta-JA spec, and input trace impedance should be controlled to 100 ohm differential for LVDS/LVPECL/HCSL to avoid reflections above 200 MHz.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for SI5330B-B00206-GMR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5330B-B00206-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330B-B00204-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330K-B00226-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330M-B00231-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI53301-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330B-B00206-GMR Specifications
| Function | Clock Fanout Buffer, Level Translator |
| Number of Inputs | 1 |
| Number of Outputs | 4 (differential LVDS) / 8 (single-ended) |
| Fanout Ratio | 1:4 |
| Maximum Output Frequency | 710 MHz |
| Supply Voltage (Vdd) | 1.8 V, 2.5 V, or 3.3 V (±10%) |
| Input Signal Type | Single-ended (CMOS/SSTL/HSTL) or Differential (LVDS/LVPECL/HCSL/CML) |
| Output Signal Type | LVDS (differential) - B00206 order code |
| Operating Temperature Range | -40 °C to +85 °C |
| Package | 24-VFQFN Exposed Pad (4x4 mm) |
| Pin Count | 24 |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (3,000 pcs) - "-GMR" suffix |
| RoHS Status | Compliant |
| Series | Si5330B |
| Sub-family | B00206 (LVDS output, configurable input) |
| Manufacturer | Skyworks Solutions Inc. (formerly Silicon Labs) |
SI5330B-B00206-GMR Pin Configuration
| Pin 1 | CLK_IN+ — Differential clock input (positive) |
| Pin 2 | CLK_IN- — Differential clock input (negative) |
| Pin 3 | VDD — Core supply voltage (1.8/2.5/3.3 V) |
| Pin 4 | GND — Ground |
| Pin 5 | OUT0+ — LVDS output 0 (positive) |
| Pin 6 | OUT0- — LVDS output 0 (negative) |
| Pin 7 | VDDO0 — Output driver supply for OUT0 |
| Pin 8 | GND — Ground |
| Pin 9 | OUT1+ — LVDS output 1 (positive) |
| Pin 10 | OUT1- — LVDS output 1 (negative) |
| Pin 11 | VDDO1 — Output driver supply for OUT1 |
| Pin 12 | GND — Ground |
| Pin 13 | OUT2+ — LVDS output 2 (positive) |
| Pin 14 | OUT2- — LVDS output 2 (negative) |
| Pin 15 | VDDO2 — Output driver supply for OUT2 |
| Pin 16 | GND — Ground |
| Pin 17 | OUT3+ — LVDS output 3 (positive) |
| Pin 18 | OUT3- — LVDS output 3 (negative) |
| Pin 19 | VDDO3 — Output driver supply for OUT3 |
| Pin 20 | GND — Ground |
| Pin 21 | SCL/MODE — Configuration control (per datasheet) |
| Pin 22 | SDA/CTRL — Configuration control (per datasheet) |
| Pin 23 | OE — Output enable |
| Pin 24 | VDD — Core supply voltage (1.8/2.5/3.3 V) |
Typical Applications
SI5330B-B00206-GMR is suitable for 6 applications: Multi-Lane SERDES Reference Clock Distribution, FPGA Reference Clock Fanout, ADC/DAC Sampling Clock Distribution, Telecom Line-Card Redundant Clock Switching, Broadcast Video/Audio Sample-Rate Conversion, Industrial Controller Timing Distribution.
Multi-Lane SERDES Reference Clock Distribution
The SI5330B-B00206-GMR fans one low-jitter reference clock into four LVDS outputs sized for multi-lane SERDES in 1 GbE to 10 GbE switches. Its sub-50 ps output-to-output skew ensures lane alignment during 10G-KR and XAUI link training, while the 710 MHz bandwidth covers 156.25 MHz GbE refs and 161.13 MHz 10G-KR rates. Designers place the part between a primary Si5341/Si5351 PLL and four PHY devices, gaining level translation from 3.3 V CMOS oscillator to 1.8/2.5 V LVDS PHYs.
Recommended
FPGA Reference Clock Fanout
The SI5330B-B00206-GMR provides low-skew LVDS clocks to multi-bank FPGAs (Xilinx, Intel, Microchip) where each bank requires its own reference. The device's input accepts single-ended or differential references typical of FPGA development boards, while its four LVDS outputs match the FPGA's LVDS clock-input standard for GT/GTX transceivers. The 24-QFN exposed pad integrates cleanly into space-constrained FPGA mezzanine cards.
Recommended
ADC/DAC Sampling Clock Distribution
The SI5330B-B00206-GMR's low additive jitter (sub-1 ps RMS typical for this family) makes it well suited to fan out one master clock to multiple high-speed ADC/DAC sampling-clock inputs in test and measurement or radar systems. With LVDS outputs it directly drives modern converter clock inputs that demand low-jitter differential signaling, while the configurable input accepts LVPECL clocks from upstream frequency synthesizers.
Recommended
Telecom Line-Card Redundant Clock Switching
Telecom line cards require glitch-free switching between primary and secondary references. The SI5330B-B00206-GMR's low-jitter performance preserves output phase noise even during source handoff, and its LVDS outputs are common in SONET/OTU framer references. Combined with an upstream Si5341/Si5351 jitter attenuator, the Si5330 forms the distribution leaf of a telecom card's redundant timing tree.
Recommended
Broadcast Video/Audio Sample-Rate Conversion
The SI5330B-B00206-GMR delivers clean LVDS clocks to professional audio/video sample-rate converters and AES3/SPDIF transceivers where jitter translates directly to audio artifacts. Its wide frequency range (1 MHz to 710 MHz) covers standard audio sample rates (48 kHz to 192 kHz), video pixel clocks (27 MHz, 74.25 MHz, 148.5 MHz), and broadcast reference rates. The exposed-pad QFN package simplifies thermal design in fanless broadcast chassis.
Recommended
Industrial Controller Timing Distribution
The SI5330B-B00206-GMR's -40 °C to +85 °C industrial temperature range and wide supply tolerance (1.8 V/2.5 V/3.3 V) suit industrial PLCs, motion controllers, and factory-automation backplanes. The buffer fans a single rugged oscillator reference to multiple MCU/CPLD timing rails without loss of phase accuracy, supporting deterministic Ethernet (EtherCAT, PROFINET) and SERCOS clock distribution in industrial networking modules.
Recommended
Recommended Products Summary
Engineering reference data for SI5330B-B00206-GMR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5330B-B00206-GM | SI5330B-B00204-GM | SI5330K-B00226-GMR | SI5330M-B00231-GMR | SI53301-B-GMR |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 24-VFQFN Exposed Pad (4x4 mm) | 24-VFQFN Exposed Pad - same | 24-VFQFN Exposed Pad - same | 24-VFQFN Exposed Pad - same | 24-VFQFN Exposed Pad - same | 24-VFQFN Exposed Pad - same |
| Fanout Ratio | 1:4 | 1:4 | 1:4 | 1:4 | 1:4 | 1:6 |
Key Differentiators
- 1:4 fanout in a small 4x4 mm QFN with integrated level translation (vs Generic 1:4 LVDS buffers from Renesas/IDT (e.g. 8T49N004))
- Wide 1 MHz to 710 MHz output frequency range with sub-1 ps additive jitter (vs PI6C557-03AQE (Diodes Incorporated 1:4 LVDS buffer))
- Same-family multiple output-standard variants share the 24-QFN footprint (vs Lock-in to a single output standard)
- Multi-source stocking via DigiKey, Mouser, Arrow, LCSC, and JLCPCB (vs Single-distributor sole-source timing ICs)
Design Notes
The 24-VFQFN exposed-pad package dissipates heat through its central EP pad. The pad must be soldered to a PCB ground copper pour with at least 16 thermal vias (0.3 mm drill, 1.0 mm pitch) on a 4x4 mm thermal land to achieve published theta-JA performance. Estimated: with 4 LVDS outputs running at 710 MHz and 100 ohm differential terminations on each, total power dissipation stays under 200 mW typical, well within the package's thermal envelope.
Route the differential clock inputs and LVDS outputs as 100 ohm differential pairs with controlled impedance (microstrip or stripline), keeping trace length match within 5 mil to preserve low skew. Place decoupling capacitors (0.1 uF ceramic) within 2 mm of every VDD and VDDOx pin, plus a bulk 1 uF ceramic near the IC. Keep clock traces away from switching power and high-current digital traces to avoid coupling.
Place the Si5330B within 25 mm of the source oscillator/PLL to avoid trace reflections above 200 MHz. For multi-output boards, fan the four LVDS outputs out symmetrically to maintain matched trace lengths; this preserves the datasheet's sub-50 ps output-to-output skew spec. Avoid 90-degree bends on any clock trace - use 45-degree mitered bends or curved routing for the best signal integrity at 710 MHz.
Do not float the OE (output enable) pin - tie it to VDD through a 10 kohm resistor or drive it actively. Floating the OE pin can leave outputs in an indeterminate state at power-up. Also, verify VDDOx (per-output driver supply) matches VDD or is properly bypassed when using single-supply designs; mismatched VDD/VVDOx can cause erratic output behavior or failure to meet the LVDS common-mode spec.
The SI5330B LVDS outputs require external 100 ohm differential termination between OUTx+ and OUTx- (closest to the receiver). For point-to-point links under 50 mm, a single resistor at the receiver end is sufficient. For longer links or backplanes, use series termination at the source plus differential termination at the receiver to maintain the eye diagram's margin. LVDS common-mode voltage is typically 1.2 V, so any DC-blocking capacitors should be rated for 50 V or more to avoid breakdown.
Compliance Information
RoHS compliant per DigiKey, Mouser, Arrow, and LCSC product listings. The Si5330 family is Pb-free and supports standard Pb-free reflow profiles (MSL 2 per JEDEC J-STD-020). REACH and full material declarations should be re-confirmed via Skyworks' latest compliance letter before EU shipment. Not AEC-Q100 qualified - this is an industrial/commercial-temp part.
