SI5330F-B00216-GMR - 1:8 LVCMOS Clock Buffer 200MHz | Skyworks
MPN: SI5330F-B00216-GMR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.05 | $4.05 |
| 10 | $3.65 | $36.50 |
| 100 | $3.25 | $325.00 |
| 500 | $2.92 | $1,460.00 |
| 1,000 | $2.6 | $2,600.00 |
SI5330F-B00216-GMR Overview
A clock buffer (or fanout buffer) is a clock-tree distribution device that takes one reference clock input and replicates it across multiple low-skew outputs, regenerating amplitude and edge-rate fidelity while isolating the source from load reflections. Clock buffers sit between the timing source (crystal oscillator, TCXO, or PLL synthesizer) and downstream loads - microprocessors, DDR memory, Ethernet PHYs, FPGAs, and high-speed data converters - forming the lowest tier of a clock-distribution tree. Other tiers above it include clock multipliers (PLL/VCXO), jitter attenuators, and frequency synthesizers.
Key specifications of the Si5330F include sub-100 fs additive RMS jitter, output-to-output skew well below 50 ps, and pin-strap output enable configuration. The input stage accepts single-ended CMOS, LVCMOS, LVPECL, LVDS, HCSL, or CML waveforms and provides on-chip termination, while each output can be individually enabled/disabled through pin straps and grouped by format selector pins. Internal PECL/LVDS level translation is performed without external coupling capacitors.
The architecture uses a precision CMOS output stage with matched rise/fall times and a low-voltage-differential input receiver to minimize jitter injection. The exposed thermal pad (EP) of the 24-QFN package ties to ground and provides a low-impedance return path for the eight switching outputs, which is essential for EMI suppression when toggling all outputs simultaneously at 200 MHz.
Typical applications include fanout for networking line cards, server and storage backplane clock distribution, industrial control boards with multiple LVCMOS loads, communications infrastructure timing trees, and any high-availability PCB where one oscillator feeds many synchronous destinations. The mixed-voltage output banks (VDDO independent per output group) make it particularly useful for legacy designs bridging 3.3 V peripherals with newer 1.8 V processors.
When designing with this device, pay careful attention to power-supply decoupling - place 0.1 µF X7R capacitors immediately adjacent to each VDD/VDDO pin and a single 10 µF bulk capacitor near the EP. Use a continuous reference-plane ground pour stitched with multiple vias beneath and around the exposed pad to keep ground bounce below jitter budget. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the Si5330 datasheet.
Drop-in alternatives for SI5330F-B00216-GMR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5330F-B00216-GMR (same form factor and footprint) — differing in Function, Number of Outputs, Package, Input Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5330F-B00215-GMR
✅ Drop-In✓ In Stock
$2.55 / Unit
View Datasheet →SI5330F-B00214-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330F-B00216-GM
✅ Drop-In✓ In Stock
$0.81 / Unit
View Datasheet →SI5330F-A00216-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330F-B00217-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5330F-B00216-GMR Specifications
| Function | Clock Fanout Buffer (Distribution) + Level Translator |
| Number of Outputs | 8 (single-ended) / 4 (differential) |
| Fanout Ratio | 1:8 |
| Output Type | LVCMOS |
| Maximum Output Frequency | 200 MHz |
| Core Supply Voltage (VDD) | 1.8 V / 2.5 V / 3.3 V |
| Output Supply Voltage (VDDO) | 1.8 V / 2.5 V / 3.3 V (independent per bank) |
| Input Compatibility | CMOS, LVCMOS, LVPECL, LVDS, HCSL, CML |
| Output-to-Output Skew | <50 ps (typical) |
| Operating Temperature Range | -40 C to +85 C |
| Package | 24-VFQFN Exposed Pad (4x4 mm) |
| Mounting Type | Surface Mount |
| MSL Level | MSL2 (per industry standard) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes / Yes (per Skyworks product page) |
SI5330F-B00216-GMR Pin Configuration
| Pin 1 | VDD — Core supply (1.8/2.5/3.3 V) |
| Pin 2 | GND — Ground |
| Pin 3 | IN — Clock input (single-ended or one half of differential) |
| Pin 4 | IN_N — Complementary clock input for differential |
| Pin 5 | SDA/MODE — Format select / control pin (per datasheet pin map) |
| Pin 6 | VDDO0 — Output bank 0 supply (1.8/2.5/3.3 V) |
| Pin 7 | OUT0 — LVCMOS output 0 |
| Pin 8 | OUT1 — LVCMOS output 1 |
| Pin 9 | VDDO1 — Output bank 1 supply |
| Pin 10 | OUT2 — LVCMOS output 2 |
| Pin 11 | OUT3 — LVCMOS output 3 |
| Pin 12 | GND — Ground |
| Pin 13 | OUT4 — LVCMOS output 4 |
| Pin 14 | OUT5 — LVCMOS output 5 |
| Pin 15 | VDDO2 — Output bank 2 supply |
| Pin 16 | OUT6 — LVCMOS output 6 |
| Pin 17 | OUT7 — LVCMOS output 7 |
| Pin 18 | VDDO3 — Output bank 3 supply |
| Pin 19 | SCL/EN — Output enable, format select (per datasheet pin map) |
| Pin 20 | MODE1 — Mode select 1 |
| Pin 21 | MODE0 — Mode select 0 |
| Pin 22 | GND — Ground |
| Pin 23 | VDD — Core supply (1.8/2.5/3.3 V) |
| Pin 24 | GND — Ground |
Typical Applications
SI5330F-B00216-GMR is suitable for 6 applications: Networking Line-Card Clock Distribution, Server and Storage Backplane Clock Trees, Industrial Control and Factory Automation, Communications Infrastructure Timing, FPGA Reference Clock Fanout, Mixed-Voltage Legacy-to-Modern Bridge.
Networking Line-Card Clock Distribution
The SI5330F-B00216-GMR fits networking line-card clock distribution by replicating one accurate reference (TCXO/OCXO) into eight low-skew outputs that feed Ethernet PHYs, switch ASICs, and SerDes blocks. Its 200 MHz ceiling and sub-100 fs additive jitter keep total output jitter within the budget required by 1G/10G Ethernet and PCIe Gen 3 reference-clock tolerance. Mixed VDDO banks (1.8 V to 3.3 V) let the same buffer feed 1.8 V PHY cores and legacy 3.3 V glue logic on the same card, eliminating level shifters. The exposed thermal pad keeps ground impedance low across simultaneous switching of all 8 outputs at 200 MHz, reducing EMI in EMI-sensitive chassis. Compared to discrete CMOS gate chains, the Si5330F improves skew from >500 ps to <50 ps and removes the need for source-termination tuning on every line.
Recommended
Server and Storage Backplane Clock Trees
The SI5330F-B00216-GMR is ideal for server and storage backplane clock distribution, where one chassis oscillator must feed RAID controllers, SAS expanders, BMCs, and DDR DIMM clock pins with tightly controlled skew. Independent VDDO rails per output bank (1.8 V, 2.5 V, 3.3 V) eliminate external level translation between modern BMC silicon (typically 1.8 V) and 3.3 V SAS expanders, reducing BOM cost and board area. The 200 MHz maximum frequency comfortably supports 100 MHz and 133 MHz DDR3 DIMM clocks plus 156.25 MHz PCIe reference clocks. Pin-strap output enables allow unused outputs to be tri-stated for unused backplane slots, simplifying inventory and keeping one BOM part number across SKUs. Use a continuous ground pour stitched with vias under the EP to meet jitter targets during simultaneous broadcast of 8 clocks.
Recommended
Industrial Control and Factory Automation
In industrial control PLC and motor-control boards, the SI5330F-B00216-GMR fans a single industrial-grade oscillator to multiple isolated I/O modules, gate-driver timing inputs, and industrial Ethernet controllers. Its -40 C to +85 C industrial temperature rating and CMOS noise immunity (LVCMOS swing with low jitter) make it tolerant of the wide thermal and EMC conditions in factory cabinets. The 1:8 ratio lets one device replace four or five 1:2/1:4 buffers, simplifying schematic maintenance and reducing part-number proliferation. Each output's tri-state enable lets the firmware (via logic gate) power-down unused I/O zones for energy saving. Compared with opto-isolated clock isolation, the LVCMOS buffer plus external digital isolator pair gives better edge fidelity at multi-MHz industrial Ethernet rates.
Recommended
Communications Infrastructure Timing
Communications infrastructure baseband and base-station clock distribution uses the SI5330F-B00216-GMR to fan a Common Public Radio Interface (CPRI) reference clock to multiple baseband DSPs, fronthaul SFP modules, and backhaul packet processors. The Si5330F accepts differential LVPECL/LVDS/HCSL inputs from the synchronizer unit and provides eight LVCMOS outputs up to 200 MHz - covering CPRI Rates 1-4 (614.4 MHz / 491.52 MHz reference multiples) and 1588 PTP grand-master clocks. Independent output-bank supply pins support mixed-voltage DSPs (typically 1.8 V core) coexisting with 3.3 V legacy FPGA fabrics on the same baseband card. The exposed pad keeps the part within thermal envelope while eight outputs toggle simultaneously at high frequency in a sealed BTS housing.
Recommended
FPGA Reference Clock Fanout
The SI5330F-B00216-GMR drives an 8-output reference-clock tree for FPGAs that require multiple clock domains: a 100 MHz logic core clock, 156.25 MHz transceiver reference, 50 MHz PCIe reference, and 200 MHz memory controller clock all sourced from the same oscillator. The Si5330F's sub-50 ps output skew guarantees time-domain alignment between TX lanes in multi-gigabit transceivers, which is critical for meeting SATA-3 / USB-3.0 / DisplayPort TX compliance margins. Independent VDDO banks let one buffer feed an FPGA's 1.8 V clock pins and an adjacent 3.3 V CPLD directly without level shifters. Compared with FPGA-internal MMCMs, the external Si5330F reduces MMCM resource use and provides cleaner jitter for the most stringent serial-link channels.
Recommended
Mixed-Voltage Legacy-to-Modern Bridge
A common challenge in legacy board refreshes is feeding 5 V-tolerant or 3.3 V peripherals with 1.8 V processors. The SI5330F-B00216-GMR simplifies this by accepting one reference clock at any input standard (CMOS/LVCMOS/LVPECL/LVDS/HCSL/CML) and dividing its 8 outputs between 1.8 V and 3.3 V rails via separate VDDO bank pins - on-chip level translation removes the level-shifters required in pure-CMOS fanout chains. Designers can keep an existing 3.3 V RTC or 3.3 V Ethernet PHY in a board while migrating the processor to 1.8 V core without a re-spin. The 200 MHz limit accommodates most legacy peripheral clocks (33 MHz PCI, 50/66 MHz Ethernet MII, 100 MHz processor memory buses). This reduces BOM count, lowers EMI (no shifters contribute additional edge rates), and lowers stack height versus discrete level-shifter ICs.
Recommended
Recommended Products Summary
Engineering reference data for SI5330F-B00216-GMR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5330F-B00215-GMR | SI5330F-B00214-GMR | SI5330F-B00216-GM | SI5330F-A00216-GMR | SI5330F-B00217-GMR |
|---|---|---|---|---|---|---|
| Package | 24-VFQFN Exposed Pad (4x4 mm) | 24-VFQFN Exposed Pad (4x4 mm) - same | 24-VFQFN Exposed Pad (4x4 mm) - same | 24-VFQFN Exposed Pad (4x4 mm) - same | 24-VFQFN Exposed Pad (4x4 mm) - same | 24-VFQFN Exposed Pad (4x4 mm) - same |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Function | 1:8 LVCMOS fanout buffer | 1:8 LVCMOS fanout buffer | 1:8 LVCMOS fanout buffer | 1:8 LVCMOS fanout buffer | 1:8 LVCMOS fanout buffer | 1:8 LVCMOS fanout buffer |
| Maximum Output Frequency | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 200 MHz |
| Core Supply Voltage | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V |
| Number of Outputs | 8 | 8 | 8 | 8 | 8 | 8 |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Order Suffix Identifier | B00216 / GMR | B00215 / GMR | B00214 / GMR | B00216 / GM | A00216 / GMR | B00217 / GMR |
Key Differentiators
- Same-package dual-sourcing via Skyworks ordering-code suffixes (vs SI5330F-B00215-GMR / B00214-GMR)
- Mixed-voltage output-bank level translation without external shifters (vs Discrete CMOS gate fanout)
- Wide input compatibility (CMOS/LVPECL/LVDS/HCSL/CML) (vs Generic CMOS-only fanout buffer)
Design Notes
Place a 0.1 µF X7R capacitor within 1 mm of every VDD and VDDO pin, and one 10 µF bulk ceramic near each supply pin cluster. The exposed thermal pad MUST be soldered to a continuous ground pour stitched with multiple thermal vias (recommended 4-9 vias, 0.3 mm drill). Without proper EP soldering, the Si5330F's ground return impedance rises and degrades output jitter budget at 200 MHz with 8 outputs toggling. Estimated: at 200 MHz with all 8 outputs loaded 5 pF each, total supply current peaks near ~70 mA, so the local decoupling must have low ESL to keep VDD ripple below 20 mV p-p.
Sequence the VDD core supply and the VDDO output-bank supplies within the datasheet window - powering VDDO before VDD can back-drive outputs. Keep the VDD and VDDO planes physically separated on the PCB to break noise coupling from switching outputs back into the sensitive input receiver. Estimated: 200 MHz × 8 toggling outputs inject noise harmonics; a ferrite-bead + capacitor Pi filter on each VDDO rail cuts ripple injection by approximately 6-10 dB.
Route the input clock traces first, matched-length within ±0.5 mm if using differential input. Keep clock output traces matched-length if your application needs tight skew downstream (otherwise let the Si5330F's internal skew matching handle it). Do not run clock traces over power-plane splits; reference them only over a continuous ground plane. For differential CLK inputs, place 100 Ω differential termination within 1 cm of the Si5330F input pins.
Each output drives ~10 mA into a lumped load, with edge rates around 1 ns - so add a 33 Ω series resistor close to the Si5330F output if the trace is longer than ~25 mm to dampen ringing. For multi-branch clock trees, match impedances at 50 Ω and use fanout stubs short relative to the rise time. Always check downstream receiver input capacitance - heavy capacitive loads (>10 pF) will increase total jitter; isolate with a buffer if needed.
Do not leave any output unconnected in high-frequency designs - unused LVCMOS outputs should be tied to a defined state through the OE pin (tri-stated) or terminated to GND via 10 kΩ, or floating stubs may resonate and corrupt adjacent outputs. Avoid mounting the Si5330F directly above a switching DC-DC converter - even on a different layer, the 8-output simultaneous switching generates broadband EMI that can couple into noisy supplies. Check that the MODE/EN pinstraps are firmly tied with no floating on boot - use 100 kΩ pull-up or pull-down resistors as required by the datasheet.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-minerals compliance per Skyworks Si5330 product page (https://www.skyworksinc.com/en/Products/Timing/CMOS-Clock-Buffers/si5330f). Not AEC-Q100 qualified - this part targets commercial/industrial -40 to +85 C applications.
