SI5332FD10368-GM1R - 6-Output Any-Frequency Clock Generator | Skyworks
MPN: SI5332FD10368-GM1R ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12 | $12.00 |
| 10 | $11.2 | $112.00 |
| 100 | $10.4 | $1,040.00 |
| 500 | $9.65 | $4,825.00 |
| 1,000 | $8.81 | $8,810.00 |
SI5332FD10368-GM1R Overview
A clock generator is a semiconductor device that produces one or more precise reference timing signals from a single input reference (typically a crystal or external clock), and falls within the broader hierarchy of timing ICs -> clock generation -> clock and timing -> integrated circuit. Clock generators sit at the foundation of every digital system, providing the timing reference that drives processors, FPGAs, serializers, memory interfaces, and data converters. Compared with discrete oscillator trees, a single programmable clock generator replaces multiple crystals and oscillators while offering finer frequency resolution.
Key differentiating features include an embedded crystal option, six independently configurable outputs, sub-200 fs RMS jitter, integrated LDOs that eliminate external supply rails, and I2C/SPI programmable configuration. Output formats include LVDS, LVPECL, HCSL, CML, and CMOS, making the Si5332 compatible with virtually any downstream logic. The 32-QFN package provides a compact 5x5 mm footprint suitable for high-density PCB designs.
Architecturally, the Si5332 separates the reference input from the synthesis core via a low-noise PLL, then routes the synthesized frequency through six independent MultiSynth fractional dividers. Each output can be independently programmed for frequency, format, and slew rate through non-volatile on-chip memory or via the serial control interface at start-up.
Typical applications include networking line cards, server and storage controllers, FPGA reference clocks, broadcast video systems, industrial automation, and any multi-rail digital platform that previously required multiple XO/VCXO components. When migrating from discrete oscillator trees, designers should budget for the I2C/SPI configuration EEPROM image and confirm jitter performance against the most stringent downstream serializer requirement.
Drop-in alternatives for SI5332FD10368-GM1R — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5332FD10368-GM1R (same form factor and footprint) — differing in Package, RoHS Status, Function, Input Reference, Number of Outputs.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5332FD10368-GM2R
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5332ED10368-GM1R
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SI5338A-B-GMR
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SI5351A-B-GTR
✅ Drop-In✓ In Stock
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View Datasheet →SI5332B-B-GMR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ZL30265LFF7
✅ Drop-In📋 Reference alternative (not in catalog)
CDCE913PWR
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View Datasheet →SI5332FD10368-GM1R Specifications
| Function | Any-frequency clock generator |
| Number of Outputs | 6 |
| Output Frequency Range | Up to 200 MHz (any frequency) |
| Output Frequency Max (per MultiSynth bank) | 333.33 MHz |
| Phase Jitter (12 kHz - 20 MHz) | 190 fs RMS (typical) |
| Input Reference | External crystal or clock; internal crystal option |
| Supported Output Formats | LVDS, LVPECL, HCSL, CML, CMOS |
| Control Interface | I2C / SPI |
| Package | 32-pin QFN (5x5 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40C to +85C (industrial) |
| MultiSynth Architecture | Yes (independent fractional dividers per output) |
| Non-volatile Configuration | Yes (on-chip EEPROM image) |
| RoHS Status | Compliant (per distributor listing) |
SI5332FD10368-GM1R Pin Configuration
| Pin 1 | VDD — Core supply voltage |
| Pin 2 | VDD_DIG — Digital supply |
| Pin 3 | GND — Ground |
| Pin 4 | XA1 — Crystal input 1 / REF clock input |
| Pin 5 | XA2 — Crystal input 2 |
| Pin 6 | REFOUT — Buffered reference output |
| Pin 7 | SDA/SDIO — I2C data / SPI data |
| Pin 8 | SCL/SCLK — I2C clock / SPI clock |
| Pin 9 | A0/CS — I2C address select / SPI chip select |
| Pin 10 | RST — Reset input (active low) |
| Pin 11 | INT — Interrupt output |
| Pin 12 | VDD_OUT0 — Output 0 supply |
| Pin 13 | OUT0P — Output 0 positive |
| Pin 14 | OUT0N — Output 0 negative |
| Pin 15 | VDD_OUT1 — Output 1 supply |
| Pin 16 | OUT1P — Output 1 positive |
| Pin 17 | OUT1N — Output 1 negative |
| Pin 18 | VDD_OUT2 — Output 2 supply |
| Pin 19 | OUT2P — Output 2 positive |
| Pin 20 | OUT2N — Output 2 negative |
| Pin 21 | VDD_OUT3 — Output 3 supply |
| Pin 22 | OUT3P — Output 3 positive |
| Pin 23 | OUT3N — Output 3 negative |
| Pin 24 | VDD_OUT4 — Output 4 supply |
| Pin 25 | OUT4P — Output 4 positive |
| Pin 26 | OUT4N — Output 4 negative |
| Pin 27 | VDD_OUT5 — Output 5 supply |
| Pin 28 | OUT5P — Output 5 positive |
| Pin 29 | OUT5N — Output 5 negative |
| Pin 30 | GND — Ground |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | EP — Exposed thermal pad (connect to GND) |
Typical Applications
SI5332FD10368-GM1R is suitable for 7 applications: Networking Line Card Clocking, FPGA Reference Clock Tree, Server and Storage Controller Timing, Broadcast Video and Imaging Systems, Industrial Automation and Robotics, Test and Measurement Instrumentation, Wireless Infrastructure and Baseband.
Networking Line Card Clocking
The SI5332FD10368-GM1R is ideal for networking line cards that require multiple precise Ethernet and SERDES reference clocks. With six independently programmable outputs and sub-200 fs RMS jitter, it can replace an entire oscillator tree while generating 156.25 MHz for 10G/25G Ethernet, 100 MHz for switch fabrics, and 125 MHz for PCIe Gen 3/4. The on-chip MultiSynth fractional dividers mean non-integer frequencies such as 161.13 MHz are achievable without pullable crystals, and the integrated LDOs remove the need for external rail conditioning.
Recommended
FPGA Reference Clock Tree
FPGA designs typically require separate references for the transceiver bank, system logic, and memory controller. The SI5332FD10368-GM1R's six outputs cover all three roles from one device, with sub-200 fs RMS jitter satisfying Xilinx UltraScale, Intel Cyclone 10, and Microchip PolarFire transceiver requirements. Each output supports independent LVDS, LVPECL, or HCSL formats, allowing direct connection to FPGA clock pins without level shifters. ClockBuilder Pro configuration enables drop-in frequency plans for common designs.
Recommended
Server and Storage Controller Timing
Server motherboards and RAID storage controllers demand low-jitter clocks for SAS, SATA, PCIe, and DDR memory interfaces. The SI5332FD10368-GM1R's 190 fs RMS jitter, six independent outputs, and CMOS/LVDS flexibility let one chip replace 4-6 discrete oscillators. Industrial temperature grade (-40C to +85C) ensures reliable operation in data-center and edge-server environments. The integrated EEPROM image boots with a known-good configuration without an external microcontroller.
Recommended
Broadcast Video and Imaging Systems
Broadcast video routers, studio cameras, and medical imaging systems need pixel-clock-grade jitter performance. The SI5332FD10368-GM1R provides sub-200 fs RMS phase jitter and supports common video rates including 74.25 MHz (720p), 148.5 MHz (1080p), and 148.35 MHz (3G-SDI) from a single reference. Its six outputs let one chip drive the FPGA fabric, serializer, audio codec, and external PHY simultaneously, reducing BOM cost and board area versus discrete XO solutions.
Recommended
Industrial Automation and Robotics
Industrial PLC, motor-drive, and robotics platforms need deterministic timing with long-term reliability. The SI5332FD10368-GM1R's -40C to +85C industrial temperature range, embedded crystal option, and wide output format support make it suitable for EtherCAT, PROFINET, and EtherNet/IP fieldbus reference clocks. Six independent outputs let one device clock the MCU, FPGA, motor-control DSP, and Ethernet PHY simultaneously while reducing BOM complexity for harsh-environment designs.
Recommended
Test and Measurement Instrumentation
Test equipment such as oscilloscopes, protocol analyzers, and arbitrary waveform generators demand ultra-low jitter references for accurate timing measurements. The SI5332FD10368-GM1R's 190 fs RMS jitter meets the requirements of mid-range oscilloscope timebases and protocol-analyzer sampling clocks. Each of its six outputs can be independently programmed via I2C, allowing the instrument to switch sample rates without re-programming an external PLL. ClockBuilder Pro tools simplify NPI integration.
Recommended
Wireless Infrastructure and Baseband
Small-cell and distributed radio unit designs require jitter-clean clocks for DSP, ADC, and DAC sampling. The SI5332FD10368-GM1R's six independently programmable outputs can drive the baseband DSP at 122.88 MHz, the ADC/DAC at 245.76 MHz, the fronthaul Ethernet at 156.25 MHz, and the local MCU at 100 MHz - all from one device. The LVDS and LVPECL outputs interface directly to RFADC/RFDAC sample-clock inputs without external buffering, simplifying RF front-end design.
Recommended
Recommended Products Summary
Engineering reference data for SI5332FD10368-GM1R — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5332FD10368-GM2R | SI5332ED10368-GM1R | SI5338A-B-GMR | SI5351A-B-GTR | SI5332B-B-GMR | ZL30265LFF7 | CDCE913PW |
|---|---|---|---|---|---|---|---|---|
| Package | 32-QFN (5x5 mm) | 32-QFN (5x5 mm) - same | 32-QFN (5x5 mm) - same | 32-QFN (5x5 mm) - same | MSOP-10 - different | 32-QFN (5x5 mm) - same | LQFP-64 - different | TSSOP-14 - different |
| Brand | Skyworks Solutions | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same | Microchip Technology - different | Texas Instruments - different |
| Number of Outputs | 6 | 6 - same | 6 - same | 4 (-33%) | 3 (-50%) | 6 - same | 6 - same | 3 (-50%) |
| Output Frequency Max | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 230 MHz |
| Phase Jitter (RMS) | 190 fs | 190 fs | 190 fs | 200 fs | 50 ps (CMOS, higher) | 190 fs | 175 fs | 60 ps (higher) |
| Output Format Support | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | CMOS only | LVDS/LVPECL/HCSL/CML/CMOS | LVDS/LVPECL/HCSL/CML/CMOS | LVCMOS |
| Control Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C | I2C / SPI | I2C / SPI | I2C |
| Embedded Crystal Option | Yes | Yes | Yes | No (external required) | No | Yes | No | No |
| Temperature Range | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Embedded crystal option eliminates external crystal (vs SI5338A-B-GMR)
- Lower phase jitter floor than TI CDCE913 (vs CDCE913PW)
- Six outputs vs Microchip ZL30265 trade-off (vs ZL30265LFF7)
Design Notes
Estimated: Place each VDD_OUT bank decoupling capacitor (10 nF + 1 uF ceramic) within 2 mm of the corresponding supply pin to minimize output jitter from rail noise. The exposed thermal pad (pin 32) must be soldered to a continuous GND plane with at least 8 thermal vias to a bottom-layer ground pour for proper heat dissipation. Keep output trace impedance at 100 ohm differential (LVDS/LVPECL) or 50 ohm single-ended (CMOS) to maintain signal integrity above 100 MHz.
Power sequencing of the core VDD before VDD_OUT banks is recommended; according to the Si5332 datasheet, powering outputs before the core can latch-up the output driver cells. Each VDD rail should be filtered with an LC pi-filter (ferrite bead + 10 uF + 0.1 uF) when fed from a shared switching regulator to prevent switching noise coupling into the output jitter floor.
For LVDS and LVPECL outputs operating above 100 MHz, route each differential pair with matched lengths (delta < 150 mil) over a continuous reference plane. Avoid 90-degree bends; use 45-degree or curved traces. When routing near a switching DC-DC converter, add a guard trace connected to GND on both sides of the differential pair to suppress common-mode noise coupling that would otherwise degrade the 190 fs jitter floor.
Do not exceed the maximum output frequency of 333.33 MHz per MultiSynth bank. Programming frequencies outside this range results in PLL unlock and invalid outputs. Always generate the configuration file using the latest ClockBuilder Pro software and verify the resulting register map against the Si5332 datasheet before committing to production. Note that the device requires a valid configuration EEPROM image to boot; without one, all outputs remain disabled.
Compliance Information
RoHS compliance confirmed via distributor listing. Industrial temperature grade (-40C to +85C); not AEC-Q100 qualified - choose Q1 suffix variant for automotive applications.
