SI53340-B-GM - 1.25GHz LVDS 2:4 Clock Buffer | Skyworks
MPN: SI53340-B-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.32 | $5.32 |
| 10 | $4.86 | $48.60 |
| 100 | $4.24 | $424.00 |
| 500 | $3.71 | $1,855.00 |
| 1,000 | $3.28 | $3,280.00 |
SI53340-B-GM Overview
Key differentiators include the 2:1 glitchless switching input mux (reduces runt pulses and phase transients during reference switchover), four LVDS outputs that meet ANSI TIA/EIA-644 standards with complementary pairs, and a wide DC-to-1250 MHz input frequency range that supports both reference clocks and high-speed data. The device is specified across -40 °C to +85 °C industrial temperature range and integrates on-chip LDOs that reject supply noise without external filtering.
The SI53340-B-GM uses Skyworks' advanced CMOS technology to guarantee 50 fs RMS typical additive jitter (12 kHz-20 MHz), 10 ps peak-to-peak output-to-output skew, and sub-picosecond propagation delay variability across process, voltage, and temperature. The integrated LDOs operate from a single 2.97 V-3.63 V supply and provide the analog blocks with a quiet internal rail, eliminating the requirement for an external clock-screened supply in most designs.
Typical applications include redundant clocking in communications infrastructure (SONET/SDH, OTN, SyncE, GbE switches), high-speed serial backplane fanout (XAUI, PCIe, SATA, SAS), multi-card clock distribution in ATCA/uTCA platforms, professional broadcast video and audio reference clocking, and FPGA/ASIC reference distribution. The LVDS outputs are well suited for point-to-point and short-haul distribution of differential clocks on controlled-impedance PCB traces.
When designing with this device, route LVDS traces as 100-Ω differential pairs with controlled impedance, keep output trace lengths matched within 150 mil to minimize skew across outputs, and decouple each VDD pin with a 0.1 μF ceramic capacitor placed within 2 mm of the pin. The exposed thermal pad must be soldered to a ground plane for electrical ground and thermal dissipation. The mux status output can be monitored to detect reference switchover events in redundant systems. This page synthesizes distributor pricing, drop-in alternatives, and practical layout guidance beyond the manufacturer datasheet.
Drop-in alternatives for SI53340-B-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI53341-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI53345-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53344-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53342-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53304-B-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI53340-B-GM Specifications
| Function | Clock Fanout Buffer (Distribution), Multiplexer |
| Input Type | LVDS (2:1 input mux) |
| Output Type | LVDS (4 outputs) |
| Number of Outputs | 4 |
| Number of Inputs | 2 (selectable via mux) |
| Input Frequency Range | DC to 1250 MHz |
| Maximum Output Frequency | 1.25 GHz |
| Supply Voltage | 2.97 V to 3.63 V |
| Additive Jitter (typ.) | 50 fs RMS (12 kHz to 20 MHz) |
| Mux Switching | Glitchless switching (internal) |
| Operating Temperature | -40 °C to +85 °C (industrial) |
| Package | 16-QFN (3x3 mm) with Exposed Pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| LVDS Standard | ANSI TIA/EIA-644 compatible |
SI53340-B-GM Pin Configuration
| Pin 1 | IN0 — LVDS input 0 (positive) - primary clock reference |
| Pin 2 | IN0_N — LVDS input 0 (negative) - primary complement |
| Pin 3 | IN1 — LVDS input 1 (positive) - backup clock reference |
| Pin 4 | IN1_N — LVDS input 1 (negative) - backup complement |
| Pin 5 | VDD — 2.97V-3.63V core supply |
| Pin 6 | GND — Digital ground |
| Pin 7 | OUT0 — LVDS output 0 (positive) |
| Pin 8 | OUT0_N — LVDS output 0 (negative) |
| Pin 9 | OUT1 — LVDS output 1 (positive) |
| Pin 10 | OUT1_N — LVDS output 1 (negative) |
| Pin 11 | VDD — Output supply (internal LDO input) |
| Pin 12 | OUT2 — LVDS output 2 (positive) |
| Pin 13 | OUT2_N — LVDS output 2 (negative) |
| Pin 14 | OUT3 — LVDS output 3 (positive) |
| Pin 15 | OUT3_N — LVDS output 3 (negative) |
| Pin 16 | GND — Ground (also exposed thermal pad) |
Typical Applications
SI53340-B-GM is suitable for 6 applications: Redundant Telecom Clock Distribution, High-Speed Serial Backplane Fanout, FPGA and ASIC Reference Distribution, Test and Measurement Instrumentation, Professional Audio and Video Reference, Industrial and Automotive Ethernet Fanout.
Redundant Telecom Clock Distribution
The SI53340-B-GM is purpose-built for redundant clocking in SONET/SDH, OTN, SyncE, and GbE switch line cards where a primary and backup reference must be fused into a single downstream clock domain. The integrated 2:1 glitchless switchover eliminates runt pulses and phase transients that would corrupt downstream PLLs or CDR circuits, meeting Telcordia GR-253 jitter requirements at the system level. Operating from DC to 1250 MHz, the buffer accepts standard telecom references of 19.44 MHz, 155.52 MHz, 156.25 MHz, 161.13 MHz, and 311.04 MHz without external dividers. The 50 fs RMS typical additive jitter over 12 kHz to 20 MHz keeps downstream jitter budgets intact across multiple fanout stages. Engineers design primary + backup reference to the two LVDS inputs and let the mux status pin drive a watchdog for audit logging.
Recommended
High-Speed Serial Backplane Fanout
In ATCA, uTCA, and AdvancedMC platforms the SI53340-B-GM distributes a single line-card reference to multiple PHY devices on the backplane. With four ANSI TIA/EIA-644 compliant LVDS outputs the part fans out to one GbE PHY, one serial RapidIO port, one SATA/SAS controller, and one FPGA transceiver reference simultaneously. The 10 ps peak-to-peak output-to-output skew range minimizes intra-card timing offsets that complicate source-synchronous interfaces like XAUI and PCIe. Each LVDS output drives 100-Ω differential PCB traces up to several inches before re-conditioning, allowing flexible placement of multiple PHY devices across a switch fabric card. The integrated LDOs reject backplane switching noise that would otherwise degrade phase noise at the transceiver reference inputs.
Recommended
FPGA and ASIC Reference Distribution
Modern FPGAs and ASICs require multiple low-jitter reference clocks for transceiver quad PLLs, memory controllers, and SerDes channels. The SI53340-B-GM fans a single low-noise reference to four LVDS clock pins on a Stratix, Virtex, Kintex, or similar high-density FPGA, keeping the same additive jitter floor across all four pins. By sourcing a 156.25 MHz LVDS reference from a single OCXO or PLL synthesizer and fanning it through the Si53340, all four reference domains see 50 fs additional jitter - enough margin for 10 GbE and CPRI optical modules. The 16-QFN 3x3 mm footprint places the buffer within 2 cm of the FPGA clock pins, minimizing PCB trace length. The exposed pad provides a low-inductance ground return that is critical for multi-GHz reference integrity.
Recommended
Test and Measurement Instrumentation
Bench-top and modular test equipment require a single high-purity reference to be fanned out to multiple instrument channels without degrading phase noise or jitter. The SI53340-B-GM provides 50 fs additive jitter, allowing the source reference (an OCXO or rubidium standard) to retain 80 percent of its phase-noise floor across all four output channels. The two input mux supports redundant reference architectures for instrumentation requiring continuous calibration. Operating from -40 °C to +85 °C without derating makes the part suitable for both rack-mounted lab instruments and field-portable ATE. The LVDS outputs interface directly with high-speed ADCs, DACs, and digitizer front-ends that demand a clean, low-jitter sampling clock.
Recommended
Professional Audio and Video Reference
Broadcast audio (AES67, Dante, AES3) and video (SMPTE 2059, PTP) systems require sub-100 fs additive jitter to maintain word-clock integrity and genlock precision across production studios. The SI53340-B-GM distributes a 48 kHz, 96 kHz, 1.024 MHz, 10 MHz, 27 MHz, or 148.5 MHz reference to multiple AV equipment inputs with only 50 fs RMS typical jitter added. The LVDS outputs are galvanically isolated by an on-card transformer or capacitive network to break ground loops between equipment chassis. The integrated glitchless 2:1 mux allows seamless primary / backup reference switchover - useful in dual-redundant master clock arrangements where AES3 audio and SMPTE video references run in parallel.
Recommended
Industrial and Automotive Ethernet Fanout
Industrial Ethernet protocols such as EtherCAT, PROFINET IRT, and TSN require sub-microsecond synchronization across multiple slave devices. The SI53340-B-GM distributes a master reference clock to up to four slave PHYs or controllers, ensuring each node receives the same time base. With -40 °C to +85 °C industrial temperature range and 50 fs additive jitter, the buffer is suitable for factory automation, robotics controllers, and substation communication equipment. The 2.97 V to 3.63 V supply permits operation from standard 3.3 V industrial rails without additional regulation. The exposed-pad QFN package is robust to industrial shock and vibration when soldered per IPC-7351 land pattern guidelines with proper via-in-pad stitching.
Recommended
Recommended Products Summary
Engineering reference data for SI53340-B-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI53341-B-GMR | SI53345-B-GM | SI53344-B-GM | SI53342-B-GM | SI53304-B-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 16-QFN (3x3 mm) with EP | 16-QFN (3x3 mm) with EP | 16-QFN (3x3 mm) with EP | 16-QFN (3x3 mm) with EP | 16-QFN (3x3 mm) with EP | 16-QFN (3x3 mm) with EP |
| Function | LVDS 2:4 fanout with glitchless mux | LVDS 1:4 fanout (no mux) | LVDS 2:4 fanout variant | LVDS 2:4 fanout variant | LVDS 4-output variant | LVDS 1:4 fanout (single input) |
| Number of Inputs | 2 (with mux) | 1 | 2 (with mux) | 2 (with mux) | 1 | 1 |
| Number of Outputs | 4 | 4 | 4 | 4 | 4 | 4 |
| Max Output Frequency | 1.25 GHz | 1.25 GHz | 1.25 GHz | 1.25 GHz | 1.25 GHz | 1.25 GHz |
| Additive Jitter (typ.) | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS |
| Supply Voltage | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| RoHS / Mux Status Output | RoHS / Mux status pin | RoHS / No mux pin | RoHS / Mux status pin | RoHS / Mux status pin | RoHS / No mux | RoHS / No mux pin |
Key Differentiators
- Integrated 2:1 glitchless input mux without external control logic (vs SI53304-B-GM)
- Same-package upgrade path within Si5334x family (vs SI53306-B-GM)
- Integrated LDOs providing high PSRR for noise-immune clock distribution (vs Discrete discrete fanout solutions)
Design Notes
Place each VDD pin decoupling ceramic (0.1 µF X7R, 6.3 V or higher) within 2 mm of the pin with a wide trace to the supply via. The exposed thermal pad must be soldered to a 4x4 grid of stitched thermal vias that share a continuous ground plane on the inner layer. LVDS pairs must be 100-Ω differential impedance with length matching to ±150 mil across output pairs to keep skew within the datasheet envelope. Per the Si5334x datasheet layout section, avoid routing LVDS traces beneath switching power converter sections to minimize capacitively coupled noise.
Terminate each LVDS output pair with a 100-Ω differential termination resistor placed as close as practical to the receiving input. For long receiver traces, place the termination at the receiver rather than at the driver output. Unused LVDS outputs should be left open with no termination; do not tie unused outputs to ground or to each other. Maintain at least 3W spacing between LVDS pairs and adjacent TTL/CMOS signals to avoid edge-coupled crosstalk that the Si5334x output stage would otherwise convert to jitter.
Estimated: input frequencies below 1 MHz are accepted by Si5334x but require careful DC-coupled driver selection because LVDS receivers expect a 1.2 V common-mode baseline; an AC-coupled input below 50 kHz will lose the bias voltage. Do not operate the Si53340-B-GM with a supply above 3.63 V - the internal LDOs will saturate and the output drivers can be damaged. Avoid hot-plugging either LVDS input: ramp the supplies first, then enable the inputs to prevent input ESD events from locking up the mux.
Compliance Information
RoHS compliant per Skyworks product page. Industrial -40 °C to +85 °C grade; AEC-Q100 not qualified - not intended for under-hood automotive.
