SN74HC165PWR - 8-Bit Parallel-Load Shift Register | TI | TSSOP-16
MPN: SN74HC165PWR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.46 | $0.46 |
| 10 | $0.38 | $3.80 |
| 100 | $0.27 | $27.00 |
| 500 | $0.21 | $105.00 |
| 1,000 | $0.17 | $170.00 |
| 3,000 | $0.14 | $420.00 |
SN74HC165PWR Overview
A shift register is a sequential logic device that converts between parallel and serial data formats, falling within the broader categories of sequential logic, digital logic IC, and finally semiconductor. The HC family (High-speed CMOS) operates at CMOS logic levels with TTL-compatible thresholds, providing low power consumption (80 uA max Icc) and balanced output drive. The '165 implements a parallel-in/serial-out (PISO) architecture: eight data inputs (A-H) are loaded asynchronously, then serially clocked out on the QH pin. This conversion allows a microcontroller with limited GPIO pins to read many switches, sensors, or buttons using only two or three pins.
Key specifications include a wide 2V-6V operating voltage range, typical propagation delay of 13 ns at 5V, ±4-mA output drive at 5V, low input current of 1 uA max, and the ability to drive up to 10 LSTTL loads. The device also features complementary outputs (Q7 and Q7-bar), direct overriding load data inputs, and a gated clock enable pin for hardware-level clock gating.
The SN74HC165 uses a master-slave flip-flop architecture with eight D-type latches feeding an internal shift register. The asynchronous load feature (active-low SH/LD-bar) overrides clocking, allowing immediate parallel capture. This dual-mode operation makes it equally suitable for capturing transient input states (button presses) and streaming serial data (sensor daisy chains). The wide VCC range supports both 3.3V and 5V systems, with TTL-compatible inputs simplifying connection to legacy logic.
Typical applications include multi-button input scanning (keypads), input expansion for microcontrollers with limited GPIO, LED matrix driving, industrial control panel scanning, and serial data daisy-chaining for sensor arrays. The cascadable serial output allows multiple '165 devices to be chained, expanding input capacity without additional microcontroller pins.
When designing with this part, consider the SH/LD-bar timing: data must be stable before SH/LD-bar returns high to avoid metastable propagation. Place a 0.1 uF decoupling capacitor close to VCC pin, and use series termination resistors on long clock lines to limit ringing.
This page synthesizes TI datasheet specifications, current distributor pricing, verified drop-in alternatives, and practical design notes beyond what a single manufacturer datasheet provides.
Drop-in alternatives for SN74HC165PWR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SN74HC165PWR (same form factor and footprint) — differing in Function, LSTTL Load Capability, Logic Family, Maximum Input Current, Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SN74HC165PW
✅ Drop-In✓ In Stock
$0.22 / Unit
View Datasheet →SN74HC165PWT
✅ Drop-In📋 Reference alternative (not in catalog)
SN74HC165PWRG4
✅ Drop-In📋 Reference alternative (not in catalog)
SN74HC165QPWRQ1
✅ Drop-In📋 Reference alternative (not in catalog)
74HC165PW
✅ Drop-In📋 Reference alternative (not in catalog)
MC74HC165ADTR2G
✅ Drop-In📋 Reference alternative (not in catalog)
SN74HC165PWR Maximum Ratings & Electrical Characteristics
| Function | Parallel-Load Shift Register (PISO/SISO) |
| Number of Bits | 8 bit |
| Logic Family | HC (High-speed CMOS) |
| Operating Voltage Range | 2 V to 6 V |
| Typical Propagation Delay (tpd) | 13 ns at 5 V |
| Maximum Quiescent Current (Icc) | 80 uA |
| Maximum Input Current | 1 uA |
| Output Drive Current | ±4 mA at 5 V |
| LSTTL Load Capability | 10 LSTTL loads |
| Output Type | Complementary (Q7 and Q7-bar) |
| Operating Temperature Range | -40 C to +125 C |
| Package | TSSOP-16 (PW) |
| Mounting Type | Surface Mount |
| MSL Level | 1 (Unlimited floor life at <30C/85% RH) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Number of Elements | 1 |
| Load Function | Asynchronous (active-low SH/LD-bar) |
SN74HC165PWR Pin Configuration
| Pin 1 | SH/LD-bar — Shift/Load input (active-low parallel load) |
| Pin 2 | CLK — Clock input (rising edge triggered) |
| Pin 3 | A — Parallel data input A |
| Pin 4 | B — Parallel data input B |
| Pin 5 | C — Parallel data input C |
| Pin 6 | D — Parallel data input D |
| Pin 7 | Q7-bar — Complementary serial output Q7 inverted |
| Pin 8 | GND — Ground reference |
| Pin 9 | Q7 — Serial data output Q7 |
| Pin 10 | SER — Serial data input for daisy-chaining |
| Pin 11 | E — Parallel data input E |
| Pin 12 | F — Parallel data input F |
| Pin 13 | G — Parallel data input G |
| Pin 14 | H — Parallel data input H |
| Pin 15 | CLK INH — Clock inhibit (active-high disables clock) |
| Pin 16 | VCC — Supply voltage (2V to 6V) |
Typical Applications
SN74HC165PWR is suitable for 6 applications: Microcontroller Input Expansion, Keypad and Button Matrix Scanning, Industrial Control and Automation, Sensor Array Daisy-Chaining, LED Display Multiplexing Drivers, Automotive Switch Input Aggregation.
Microcontroller Input Expansion
The SN74HC165PWR expands microcontroller GPIO by 8x using only 3 MCU pins (SH/LD-bar, CLK, and Q7). With a typical tpd of 13 ns at 5V and TTL-compatible input thresholds, it captures parallel switch or sensor states and serializes them out to MCUs with limited pin count. This enables designs with many buttons or switches on STM32, PIC, or MSP430 platforms without I/O expander overhead.
Recommended
Keypad and Button Matrix Scanning
The SN74HC165PWR's asynchronous parallel-load feature (active-low SH/LD-bar) deterministically latches transient button states before serializing them to the MCU. With 1 uA max input current and ±4 mA output drive, it directly interfaces with mechanical switches without external pull-ups in many cases. This application is critical for industrial control panels and human-machine interfaces.
Recommended
Industrial Control and Automation
In industrial PLC and control panels, the SN74HC165PWR aggregates multiple 24V-tolerant sensor inputs via external resistor networks, serializing them for a central MCU. The -40C to +125C operating range and 80 uA quiescent current suit factory floor environments. Its wide 2V-6V VCC range supports both 3.3V and 5V industrial logic systems with reliable noise margins.
Recommended
Sensor Array Daisy-Chaining
The SN74HC165PWR's SER input and Q7/Q7-bar complementary outputs allow multiple chips to be cascaded, expanding input capacity to 16, 24, or 32 sensors while using only 3 MCU pins. The 13 ns propagation delay at 5V keeps clock skew manageable across multi-chip chains. This is ideal for distributed sensor arrays in environmental monitoring or building automation.
Recommended
LED Display Multiplexing Drivers
The SN74HC165PWR can serve as the input side of a multiplexed LED display system, reading row-selection switches while SN74HC595 chips drive the column outputs. With complementary Q7/Q7-bar outputs and ±4 mA drive, it provides flexible timing control. Cascaded configurations allow 7-segment or dot-matrix displays with minimal MCU pin usage.
Recommended
Automotive Switch Input Aggregation
The SN74HC165PWR's AEC-Q100-qualified variant (SN74HC165QPWRQ1) aggregates automotive switch inputs for body controllers, instrument clusters, and HVAC panels. The TSSOP-16 footprint survives automotive thermal cycling, while the wide VCC range tolerates 12V battery transients when properly protected. Multiple chips daisy-chain via SER to handle steering wheel buttons and door switches.
Recommended
Recommended Products Summary
Engineering reference data for SN74HC165PWR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74HC165PW | SN74HC165PWT | SN74HC165PWRG4 | SN74HC165QPWRQ1 | 74HC165PW | MC74HC165ADTR2G |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Nexperia | onsemi |
| Package | TSSOP-16 (PW) | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same |
| Logic Family | HC (2V to 6V) | HC (2V to 6V) | HC (2V to 6V) | HC (2V to 6V) | HC (2V to 6V) | HC (2V to 6V) | HC (2V to 6V) |
| Bits | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit |
| Automotive Grade (AEC-Q100) | No | No | No | No | Yes | No | No |
| Output Drive (5V) | ±4 mA | ±4 mA | ±4 mA | ±4 mA | ±4 mA | ±4 mA (typ) | ±4 mA (typ) |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C (AEC-Q100) | -40C to +125C | -55C to +125C |
| Packaging Form | Tape & Reel (3000) | Tube/Tray | Tape & Reel (250) | Tape & Reel (3000) | Tape & Reel (3000) | Tube/Tray | Tape & Reel (2500) |
Key Differentiators
- Asynchronous parallel-load capability with SH/LD-bar (vs SN74HC164 (8-bit SIPO without parallel inputs))
- Gated clock with CLK INH pin (vs SN74HC165 generic variants without CLK INH)
- Complementary Q7/Q7-bar outputs (vs Single-ended serial-output shift registers)
Design Notes
Estimated power consumption: at 5V VCC with 80 uA max quiescent current, idle power is approximately 0.4 mW. When driving dynamic loads at 1 MHz with all outputs toggling, dynamic current can reach several mA. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of the VCC pin (pin 16) and a bulk 1-10 uF capacitor on the supply rail. The TSSOP-16 package has low thermal resistance (around 100 C/W) so no special heatsinking is required for typical digital switching loads.
Critical timing pitfall: SH/LD-bar must return HIGH before the first rising CLK edge after a parallel load, otherwise the loaded data may be overwritten by a spurious shift. Hold SH/LD-bar LOW for at least one CLK-to-Q7 propagation delay (13 ns at 5V) before releasing. Conversely, SH/LD-bar must stay HIGH during all shift operations to prevent re-loading. Violating this timing causes intermittent data corruption that is notoriously hard to debug. Use a setup time of t_SU = 20 ns minimum as a design margin.
For clock traces longer than 50 mm, add a 33-100 ohm series termination resistor near the CLK driver to dampen ringing. The complementary Q7/Q7-bar outputs provide a built-in differential pair - route them as a length-matched pair if you need skew-controlled timing. When daisy-chaining multiple '165 chips, keep the SER-to-Q7 trace under 25 mm shorter than the maximum to avoid setup-time violations at high clock rates (above 25 MHz).
TSSOP-16 has a 0.65 mm pin pitch requiring fine PCB capability (6 mil traces/spaces minimum). Use a ground plane on the layer directly under the IC for shielding and thermal spreading. Solder paste stencil apertures of 0.3 mm x 1.5 mm with 0.1 mm thickness work well for reflow profiles following IPC/JEDEC J-STD-020. Hand-soldering is feasible but requires a fine-tip iron and flux - consider using a hot-air rework station for prototypes.
Compliance Information
Standard SN74HC165PWR is not AEC-Q100 qualified - choose SN74HC165QPWRQ1 for automotive. RoHS/REACH compliance per TI product page. Pb-free matte tin (Sn) lead finish.
