10AS032E4F27I3SG vs 10AS032E4F27I3LG Comparação
Comparação detalhada lado a lado de 10AS032E4F27I3SG por Intel e 10AS032E4F27I3LG por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 10AS032E4F27I3SG | 10AS032E4F27I3LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $1.465,00 | $1.085,10 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Arria 10 SX | — |
| Device Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 320,000 | 320,000 |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Clock Frequency | Up to 1.5 GHz | 1.5 GHz |
| Process Technology | 20 nm | 20 nm |
| Core Voltage (typ.) | 0.9 V | — |
| Encapsulamento | 672-pin FCBGA (Flip-Chip BGA), 27 x 27 mm | 672-pin FCBGA (F27, 27x27 mm) |
| Terminal Form | Ball | — |
| Number of Terminals | 672 | — |
| Operating Temperature Grade | Industrial (-40C to +100C junction) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Compliance / Lead-Free | RoHS compliant, lead-free | — |
| Status do ciclo de vida | Active | — |
| FPGA Architecture | SRAM-based, volatile configuration | — |
| Family | — | Arria 10 SX SoC FPGA |
| Hard Processor Subsystem (HPS) | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Speed Grade | — | E4 (-4, mid-tier) |
| Temperature Grade | — | Industrial (-40C to +100C) |
| Status RoHS | — | Compliant |
| Lead-Free | — | Yes |
| Nível MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Transceivers | — | Up to 24 channels, up to 14.1 Gbps (family-level) |
| DSP Blocks | — | Hardened floating-point DSP (family-level) |
| Memory Interfaces | — | DDR3 / DDR4 with hard controllers (family-level) |
| Configuration Method | — | JTAG, ASx4, FPP (family-level) |