10AX090U3F45E2SG vs 10AX090U3F45E2LG Comparação
Comparação detalhada lado a lado de 10AX090U3F45E2SG por Intel e 10AX090U3F45E2LG por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 10AX090U3F45E2SG | 10AX090U3F45E2LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $3.295,00 | $6.900,00 |
| Family | Arria 10 GX | — |
| Logic Elements | 900,000 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | [DATA_NEEDED: ALM count] |
| Embedded Memory (bits) | 59,234,304 | — |
| DSP Blocks | 1,560 | [DATA_NEEDED: DSP block count] |
| User I/O Count | 480 | — |
| Transceivers | [DATA_NEEDED: transceiver count] | — |
| Max Transceiver Data Rate | 28.05 Gbps | — |
| Process Technology | 20 nm | 20nm TSMC |
| Core Voltage (SmartVID) | 0.85 V to 0.95 V | — |
| Encapsulamento | 1932-ball FCBGA (F45) | 1932-BBGA, FCBGA |
| Ball Pitch | 1.0 mm | — |
| Speed Grade | U3 (extended industrial) | — |
| Temperatura de operação | -40C to +100C (extended industrial, 'E2') | — |
| Configuration Scheme | Active Serial x4 / JTAG | — |
| Hard Memory Controller | DDR4 with ECC, up to 17.4 Gbps | — |
| Hard IP Blocks | PCIe Gen3, 10GbE MAC, SmartVID controller | — |
| Tipo de montagem | Surface Mount (BGA) | — |
| Status RoHS | Compliant | Compliant |
| Nível MSL | [DATA_NEEDED: MSL rating] | — |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded Memory Bits | — | 59,234,304 bits |
| Number of Transceivers | — | 48 transceiver macro channels (480 I/O references) |
| Maximum Transceiver Data Rate | — | [DATA_NEEDED: exact Gbps] |
| Hard Memory Controllers | — | Yes - DDR4, DDR3, QDR IV, RLDRAM 3 with hardened PHY |
| Hard PCIe Controllers | — | PCIe Gen3 x8 |
| Hard Ethernet MACs | — | 10GbE and 100GbE MACs |
| Number of I/O Banks | — | [DATA_NEEDED: bank count] |
| Maximum User I/O Pins | — | 480 (per DigiKey listing) |
| Package Pin Pitch | — | [DATA_NEEDED: pitch] |
| Operating Temperature Grade | — | OTHER / Extended (per Partstack listing) |
| Configuration Method | — | Serial (active/passive) and parallel via Quartus Prime |
| Development Tool | — | Intel Quartus Prime |