10AX090U4F45E3LG vs 10AX090S4F45E3LG Comparação
Comparação detalhada lado a lado de 10AX090U4F45E3LG por Intel e 10AX090S4F45E3LG por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 10AX090U4F45E3LG | 10AX090S4F45E3LG |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7.147,87 | $4.582,63 |
| Manufacturer | Altera | — |
| Current Brand | Intel | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Family | Arria 10 GX | Arria 10 GX (10AX090) |
| Logic Elements | 900000 | — |
| User I/O | 480 | — |
| Embedded Memory | 59234304 bit | 59,234,304 bits (~7.4 Mbytes) |
| Encapsulamento | 1932-BBGA, FCBGA | 1932-ball FCBGA (F45, 45 mm) |
| Terminal Count | 1932 | — |
| Terminal Form | Ball | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | — |
| DSP Block Count | [DATA_NEEDED: DSP block count] | — |
| Temperature Grade | [DATA_NEEDED: temperature grade] | Industrial (LG suffix) |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | -3 (enhanced, E3) |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count] |
| Maximum User I/O Pins | — | 624 |
| Ball Pitch | — | 1.0 mm |
| Transceivers | — | Up to 28.05 Gbps backplane-capable |
| Lead-Free / Halogen-Free | — | Yes (LG suffix indicates lead-free, no heat spreader) |
| Process Node | — | 20 nm TSMC |
| DSP Blocks | — | [DATA_NEEDED: DSP slice count] |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Configuration | — | FPGA - Field Programmable Gate Array |