5CSEBA6U23I7LN vs 5CSXFC2C6U23I7LN Comparação
Comparação detalhada lado a lado de 5CSEBA6U23I7LN por Intel e 5CSXFC2C6U23I7LN por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 5CSEBA6U23I7LN | 5CSXFC2C6U23I7LN |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $184,83 | $198,00 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SX |
| Logic Elements | 110,000 | 25K |
| Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum CPU Clock | 925 MHz | — |
| Encapsulamento | 672-pin UBGA (UBG-672) 23x23 mm | 672-pin UBGA (23x23 mm) |
| Tipo de montagem | Surface Mount (BGA) | — |
| Speed Grade | I7 (fast) | — |
| Temperature Range | Industrial (-40C to +100C junction) | — |
| Suffix L | Lead-free | — |
| Suffix N | Tray packaging | — |
| Status RoHS | Compliant (lead-free suffix) | Compliant |
| Hard Memory Blocks | [DATA_NEEDED: total M10K and MLAB bits] | — |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP block count] | [DATA_NEEDED: number of DSP blocks] |
| HPS Peripherals | Gigabit Ethernet, USB 2.0 OTG, CAN, SPI, I2C, UART, SD/SDIO | — |
| Configuration Mode | JTAG and Active Serial (AS) | — |
| Process Node | TSMC 28 nm low-power | — |
| Design Toolchain | Intel Quartus Prime + SoC EDS | — |
| Device Type | — | System-on-Chip (SoC) FPGA |
| HPS Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Clock Frequency | — | 925 MHz |
| Process Technology | — | 28 nm low-power |
| Temperature Grade | — | Industrial (I7) |
| Estilo de montagem | — | Surface Mount (SMD/SMT) |
| Number of Cores | — | 2 |
| Core | — | ARM Cortex A9 |
| Block RAM | — | [DATA_NEEDED: total Kbits] |
| PLLs | — | [DATA_NEEDED: total PLLs] |
| Transceivers | — | [DATA_NEEDED: transceiver count and rate] |