ATF22V10C-5JC vs ATF22V10C-5JX Comparação

Comparação detalhada lado a lado de ATF22V10C-5JC por Microchip Technology e ATF22V10C-5JX por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Microchip Technology
ATF22V10C-5JC ATF22V10C-5JC - 500-Gate EE PLD, 10 Macrocells, 5ns | Microchip

ATF22V10C-5JC - 500-Gate EE PLD, 10 Macrocells, 5ns | Microchip

ATF22V10C-5JC ✓ Ativo
Microchip Technology
ATF22V10C-5JX ATF22V10C-5JX - 5ns 500-Gate EE PLD | Microchip Technology

ATF22V10C-5JX - 5ns 500-Gate EE PLD | Microchip Technology

ATF22V10C-5JX ✓ Ativo

Comparação de especificações

Parâmetro ATF22V10C-5JC ATF22V10C-5JX
Marca Microchip Technology Microchip Technology
Categoria Logic ICs Logic ICs
Status do ciclo de vida Ativo Ativo
Device Type EE PLD (Electrically Erasable Programmable Logic Device) Electrically erasable programmable logic device (EE PLD)
Family ATF22V10C / 22V10 —
Macrocells 10 macrocells —
Total Gates 500 gates —
Propagation Delay (tPD) 5 ns (min, -5 speed grade) —
Max Frequency 166 MHz (per FindIC listing of device attributes) —
Tensão de alimentação 5 V nominal 5 V
Supply Tolerance (Commercial) 5 V +/- 5% —
Supply Tolerance (Military/Industrial) 5 V +/- 10% —
Power-Down Current 10 uA (typical) —
Technology CMOS with electrically erasable Flash configuration memory —
Input Latch Feature Yes - holds inputs to previous logic states —
Fusemap Compatibility JEDEC GAL22V10 fusemap compatible (pin-to-pin) —
Encapsulamento 28-PLCC (QCCJ), J-lead, 11.51 mm x 11.51 mm 28-pin PLCC (11.51 mm x 11.51 mm)
Package Code QCCJ —
Terminals 28 J-bend (J-lead) terminals —
Package Shape Square —
Temperature Grade Commercial —
Tipo de montagem Surface Mount Surface mount
Programmable Yes - in-circuit electrically erasable —
Status RoHS [DATA_NEEDED: RoHS compliance statement] [DATA_NEEDED: RoHS status]
Datasheet Document ATF22V10C(Q) Complete Datasheet (Microchip doc0735 PDF) —
Logic Family — Simple programmable logic device (SPLD)
Configuration Memory — Electrically erasable Flash memory
Macrocell Count — 10 macrocells
Logic Capacity — 500 gates
Maximum Frequency — 166 MHz
Propagation Delay — 5 ns speed grade
Typical Low Power Dissipation — 10 uA
Lead Configuration — J-lead
Power-Down Control — Optional pin-controlled power-down
Power-Down PLCC Pin — Pin 5
REACH Status — [DATA_NEEDED: REACH status]
AEC-Q100 Qualification — [DATA_NEEDED: AEC-Q100 qualification]
Faixa de temperatura de operação — [DATA_NEEDED: operating temperature range]

Fichas técnicas e recursos

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