ATMEGA128-16MUR vs ATMEGA128L-8MNR Comparação
Comparação detalhada lado a lado de ATMEGA128-16MUR por Microchip Technology e ATMEGA128L-8MNR por Microchip Technology. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Microchip Technology
ATMEGA128-16MUR - 8-bit AVR MCU 128KB 16MHz | Microchip
ATMEGA128-16MUR ✓ AtivoMicrochip Technology
ATMEGA128L-8MNR - 8-bit AVR MCU 128KB Flash 64-QFN | Microchip
ATMEGA128L-8MNR ✓ AtivoComparação de especificações
| Parâmetro | ATMEGA128-16MUR | ATMEGA128L-8MNR |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoria | Microcontrollers | Microcontrollers |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,40 | $4,55 |
| Core Architecture | 8-bit AVR RISC | 8-bit AVR RISC |
| Core Size | 8-bit | — |
| Frequência máxima de clock | 16 MHz | — |
| Flash Memory | 128 KB (64K x 16) | — |
| SRAM | 4 KB | 4 KB |
| EEPROM | 4 KB | 4 KB |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| ADC Channels | 8 channels | — |
| ADC Resolution | 10-bit | — |
| Timers/Counters | 2 x 8-bit, 2 x 16-bit | — |
| PWM Channels | Yes (hardware PWM) | — |
| Communication Interfaces | 2 x USART, SPI, TWI (I2C) | — |
| JTAG Debug | Yes (on-chip debug and boundary scan) | — |
| I/O Pins | 53 | — |
| External Memory Support | Up to 64 KB | — |
| Sleep Modes | 6 | — |
| Encapsulamento | 64-VFQFN (9x9 mm) exposed pad | 64-QFN (9x9 mm), VFQFN with exposed pad |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Throughput | Up to 16 MIPS | — |
| Clock Speed | — | 8 MHz |
| Flash Program Memory | — | 128 KB (64K x 16) |
| Tensão de alimentação | — | 2.7 V to 5.5 V |
| Largura do barramento de dados | — | 8 bit |
| I/O Ports | — | 53 I/O lines |
| ADC | — | 8-channel, 10-bit |
| Interface Types | — | JTAG, SPI, TWI (I2C), USART x2 |
| Instructions | — | 133 instructions, most single-cycle |
| Number of Terminals | — | 64 |
| Programming Method | — | ISP (In-System), IAP (In-Application), JTAG |
| On-Chip Debug | — | JTAG on-chip debugging |
| Lifecycle Stage | — | ACTIVE |