EP1810GC-35AB vs EP1810JI-35 Comparação
Comparação detalhada lado a lado de EP1810GC-35AB por Altera e EP1810JI-35 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810GC-35AB | EP1810JI-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,95 | $18,60 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | — |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Device Family | — | Classic EPLD |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Encapsulamento | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Tensão de alimentação | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Tipo de montagem | — | Through-Hole (J-lead) |
| Nível MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |