EP1810LI-25 vs EP1810LC-25T Comparação
Comparação detalhada lado a lado de EP1810LI-25 por Altera e EP1810LC-25T por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810LI-25 | EP1810LC-25T |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,95 | $8,40 |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Usable Gates | 900 | Approx. 900 |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | 5 V nominal |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | 16 |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| Encapsulamento | 68-pin PLCC (J68, J-Lead) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | — |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Lead-Free Status | unknown | — |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Temperatura de operação | — | 0 °C to +70 °C (commercial) |
| Tipo de montagem | — | Surface Mount |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |