EP1K30TC144-1N vs EP1K30TI144-2N Comparação
Comparação detalhada lado a lado de EP1K30TC144-1N por Altera e EP1K30TI144-2N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1K30TC144-1N | EP1K30TI144-2N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $11,50 | $25,00 |
| Series | ACEX-1K | ACEX-1K |
| Number of Logic Elements (LEs) | 1,728 | — |
| Typical Gates | 30,000 | — |
| Number of Logic Array Blocks (LABs) | 216 | [DATA_NEEDED: LAB count] |
| Embedded Memory (EAB) | 24,576 bits (6 EABs) | — |
| Number of User I/O | 102 | — |
| Number of I/O Banks | 4 | — |
| Package Type | 144-LQFP (TQFP) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Core Voltage | 2.5 V | — |
| I/O Voltage | 3.3 V (LVCMOS/LVTTL); 2.5 V tolerant | — |
| Temperatura de operação | [DATA_NEEDED: operating temperature range] | — |
| Process Technology | 0.18 µm SRAM | 0.22 µm CMOS SRAM |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) + serial/parallel passive | — |
| PLLs | 6 (per device family) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant (per Utmel product note) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Nível MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements / Cells | — | 1728 |
| Typical Gate Count | — | 30,000 gates |
| Embedded Memory (RAM bits) | — | 24,576 bits |
| Maximum User I/O | — | 102 |
| Number of Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count] |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V |
| Speed Grade | — | -2 |
| Operating Temperature Grade | — | Industrial |
| Faixa de temperatura de operação | — | -40 °C to +100 °C ambient |
| Encapsulamento | — | 144-pin LQFP |
| Lead Pitch | — | 0.5 mm |
| Configuration Interface | — | JTAG (IEEE 1149.1), serial passive/active |