EP1S10F780I6N vs EP1S10F780C6N Comparação
Comparação detalhada lado a lado de EP1S10F780I6N por Intel e EP1S10F780C6N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1S10F780I6N | EP1S10F780C6N |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $98,75 | $205,00 |
| Family | Stratix | Stratix |
| Logic Elements | 10,570 | — |
| Logic Array Blocks (LABs) | 1,057 | — |
| User I/Os | 426 | — |
| Embedded RAM (Total) | 920,448 bits | — |
| M512 Blocks | 94 (32 x 18 bits each) | — |
| M4K Blocks | 60 (128 x 36 bits each) | — |
| M-RAM Blocks | 1 (4 Kbit) | — |
| PLLs | 6 | — |
| Clock Outputs | 16 | — |
| DSP Blocks | 12 | — |
| Transceiver Channels | 12 (not populated on I6 speed grade) | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| I/O Voltage (VCCIO) | 1.5 V, 1.8 V, 2.5 V, 3.3 V (per bank) | — |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Temperatura de operação | -40 °C to +100 °C (industrial) | 0 C to +85 C (Commercial) |
| Speed Grade | -6 (6.0 ns core clock period) | — |
| Encapsulamento | 780-ball FineLine BGA, 29 x 29 mm, 1.0 mm pitch | FBGA-780 (29 x 29 mm, 1.0 mm pitch) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Nível MSL | 3 (168 hours) | [DATA_NEEDED: MSL rating] |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (LEAD FR finish per AiPCBA datasheet) |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Logic Family | CMOS | CMOS |
| Supply Voltage Nominal | 1.5 V | — |
| Logic Elements (LEs) | — | 10,570 |
| Configurable Logic Blocks (CLBs) | — | 1,200 |
| Embedded Memory | — | 920 Kbit (TriMatrix) |
| Core Supply Voltage | — | 1.5 V |
| I/O Supply Voltage | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V LVTTL/LVCMOS, LVDS) |
| Maximum Internal Clock Frequency | — | 450.05 MHz |
| Pin / Ball Count | — | 780 |
| User I/O Count | — | 426 (per FindIC) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous |
| Lead Finish | — | SnPb (LEAD FR / non-RoHS variant) |