EP20K200RC208-3V vs EP20K200RC208-1X Comparação

Comparação detalhada lado a lado de EP20K200RC208-3V por Altera e EP20K200RC208-1X por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP20K200RC208-3V EP20K200RC208-1X
Marca Altera Intel
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Ativo Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $0,00 $35,80
Series APEX-20K —
Number of Logic Elements / Cells 8320 —
Number of Gates 200000 typical —
Total RAM Bits 106496 —
Number of User I/Os 144 —
Supply Voltage Range 2.375 V to 2.625 V —
Maximum Internal Frequency 167 MHz —
Process Technology 0.22 um 0.18 µm CMOS
Encapsulamento / Caixa 208-BFQFP Exposed Pad —
Supplier Device Package 208-RQFP (28x28) —
Número de pinos 208 —
Tipo de montagem Surface Mount Surface Mount (gull-wing leads)
Core Architecture MultiCore, combining LUT logic, product-term logic, and embedded memory —
Interconnect Four-level hierarchical FastTrack Interconnect —
Faixa de temperatura de operação [DATA_NEEDED: operating temperature range] —
Speed Grade [DATA_NEEDED: exact speed grade suffix interpretation] -1X (1.8 V core, PQFP-208 pinout)
Status RoHS [DATA_NEEDED: RoHS status] Compliant (lead-free PQFP package)
Core Supply Current [DATA_NEEDED: core supply current] —
Configuration Interface [DATA_NEEDED: configuration interface details] IEEE 1149.1 JTAG, serial, passive parallel (PPA), EPC configuration devices
Family — APEX-20KE
Logic Elements — 8,320 cells
Typical Gate Count — 200,000 gates
Embedded RAM Bits — 106,496 bits
Embedded RAM Blocks (ESBs) — 4 lanes / 52 ESBs
Maximum User I/O Pins — 144 (PQFP-208 variant)
Core Voltage — 1.8 V (±5%)
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS, GTL+
Encapsulamento — 208-pin PQFP / RQFP (28x28 mm), 0.5 mm pitch
Temperatura de operação — 0 °C to +85 °C (commercial)
MultiCore Architecture — LUT logic + product-term logic + embedded memory
PLL Count — 4 enhanced PLLs (with programmable phase shift)
Moisture Sensitivity Level — MSL 3 (per JEDEC J-STD-020, applicable to PQFP)

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