EP20K400CB652C9ES vs EP20K400CB652C9N Comparação
Comparação detalhada lado a lado de EP20K400CB652C9ES por Intel e EP20K400CB652C9N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP20K400CB652C9ES | EP20K400CB652C9N |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $195,00 | $195,00 |
| Series | APEX 20KC | EP20K400 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Embedded Memory (Bits) | 212992 | — |
| Number of User I/O | 488 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Number of Logic Array Blocks | 1040 | — |
| Maximum Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS | — |
| Faixa de temperatura de operação | 0°C to +85°C (Commercial) | 0 °C to +85 °C (Commercial) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Encapsulamento / Caixa | 652-BGA | — |
| Nível MSL | 3 (168 Hours) | — |
| Packaging | Tray | — |
| Programmability Type | In-system programmable (SRAM-based) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PLL | Yes (4-phase) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Unknown (legacy Altera part - verify with distributor) |
| Device Type | — | Programmable Logic Device (SOPC FPGA) |
| Architecture | — | MultiCore (LUT logic + Embedded System Blocks) |
| System Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Maximum User I/Os | — | 502 |
| Total Memory Bits | — | 212,992 (per chip) |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.0 ns |
| Logic Family | — | CMOS |
| Core Process Technology | — | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V |
| Encapsulamento | — | BGA-652 (Plastic Ball Grid Array, 652 balls) |
| Configuration Interface | — | IEEE 1149.1 JTAG, serial passive parallel async |