EP2A25F672C9N vs EP2A25F672C9 Comparação
Comparação detalhada lado a lado de EP2A25F672C9N por Intel e EP2A25F672C9 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP2A25F672C9N | EP2A25F672C9 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | NRND |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $195,00 | $700,00 |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24320 | — |
| System Gates | Approx. 900000 | — |
| Maximum User I/O | 492 | — |
| Operating Frequency | 236 MHz | — |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V (nominal 1.5 V) | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Encapsulamento | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch | 672-ball FCBGA (FineLine BGA) |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount |
| Seated Height (max) | 2.100 mm | — |
| Propagation Delay | 2.23 ns | 1.69 ns |
| Logic Family | CMOS | CMOS |
| Temperatura de operação | 0 °C to +85 °C (commercial, C9 grade) | 0°C to 85°C (Commercial) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport | — |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | — |
| Configuration Interface | Serial / Parallel PROM, JTAG, passive parallel (enhanced) | — |
| Embedded Memory | Enhanced System Blocks (ESBs) for dual-port RAM | ESBs for dual-port RAM, ROM, FIFO |
| Design Software | Quartus II (v5.1 or later) | — |
| Status RoHS | Compliant (per distributor listings) | [DATA_NEEDED] |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Tensão de alimentação | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |