EP2A40F1020C9 vs EP2A70F1020C9 Comparação
Comparação detalhada lado a lado de EP2A40F1020C9 por Intel e EP2A70F1020C9 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP2A40F1020C9 | EP2A70F1020C9 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $160,00 | $132,80 |
| Family | APEX II | APEX II (APII) |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1,500,000 (1.5M) | — |
| Macrocells | 2,560 | — |
| User I/Os | 735 | — |
| Encapsulamento | 1020-pin FC-FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch | 1020-ball FBGA (FineLine BGA) |
| Process Technology | 0.15-µm CMOS, up to 8-layer all-layer copper metal | — |
| Core Voltage | 1.5 V | — |
| Maximum Internal Frequency | 366 MHz | — |
| Propagation Delay | 1.55 ns | — |
| Logic Family | CMOS | — |
| Temperatura de operação | 0°C to 85°C (Commercial) | — |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount |
| I/O Standards Supported | LVTTL, LVCMOS, PCI 32/64-bit, PCI-X 133 MHz, AGP, CTT, SSTL-2 / SSTL-3 Class I & II, GTL+, HSTL Class I & II | — |
| Embedded Memory | ESBs (Embedded System Blocks) supporting dual-port RAM, CAM, and product-term logic | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gates | — | ~70,000 gates |
| User I/O Pins | — | 735 |
| Speed Grade | — | -9 (fastest) |
| Operating Temperature Grade | — | Commercial (C) |
| Configuration Method | — | JTAG / passive serial / passive parallel |
| Core Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal value] |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO nominal value] |
| On-chip Memory | — | EABs (Embedded Array Blocks) |
| Embedded Multipliers | — | Yes (DSP blocks in LABs) |
| Nível MSL | — | 3 (JEDEC J-STD-020) |