EP610DC-20 vs EP610DI-25 Comparação
Comparação detalhada lado a lado de EP610DC-20 por Intel e EP610DI-25 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP610DC-20 | EP610DI-25 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $15,85 | $9,95 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | — |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 (bidirectional) | 16 (bidirectional) |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 25 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Temperatura de operação | 0 °C to 70 °C (commercial) | Industrial (per "I" suffix) |
| Encapsulamento | 24-pin Ceramic DIP (CDIP-24) with UV window | — |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Tipo de montagem | Through-hole | Through-Hole (DIP) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Part Family | — | Classic EPLD |
| Macrocells | — | 16 |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Contagem de pinos | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |