EP610IDC-15 vs EP610IDC-10 Comparação
Comparação detalhada lado a lado de EP610IDC-15 por Intel e EP610IDC-10 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP610IDC-15 | EP610IDC-10 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,95 | $8,85 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal) |
| Temperatura de operação | 0C to +70C (commercial) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| Encapsulamento | 24-pin CerDIP (ceramic DIP) | — |
| Tipo de montagem | Through-hole | Through-hole |
| I/O Pins | 24 (per package; macrocell-programmable) | 20 |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| Status RoHS | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| Dedicated Inputs | — | 4 |
| Faixa de temperatura de operação | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |