EP9100C-30 vs EP910DI-30 Comparação

Comparação detalhada lado a lado de EP9100C-30 por Altera e EP910DI-30 por Rochester Electronics. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP9100C-30 EP910DI-30
Marca Altera Rochester Electronics
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete NRND
Status do estoque In Stock In Stock
Preço unitário (USD) $7,95 $17,60
Family Altera Classic EPLD Classic EPLD (Altera EP910 series)
Logic Density 900 usable gates (approx.) —
Macrocells 48 —
Flip-Flops 24 —
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns —
Maximum Toggle Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
I/O Standard TTL-compatible —
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Temperatura de operação 0C to +70C (commercial) -40C to +85C (industrial)
Encapsulamento 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (ceramic DIP, 40-pin with UV window)
Programming Method JEDEC via Altera APU or compatible programmer —
Tipo de montagem Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole (DIP)
Status RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance status]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) —
Product Type — UV-Erasable Programmable Logic Device (EPLD)
Macrocell Count — 24
Propagation Delay (tpd) — 30 ns
Maximum Toggle Frequency (fmax) — 62 MHz
Dedicated I/O Pins — 12 (12 input + 12 output)
Output Enable Pins — 2
Contagem de pinos — 40
Programmable Logic Element — JEDEC fuse map (3rd-party programmer)
Manufacturer (Original) — Altera (now Intel PSG)
Current Distributor / Authorized Aftermarket — Rochester Electronics, LLC

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