EPC20LC20U vs EPC16UC88 Comparação
Comparação detalhada lado a lado de EPC20LC20U por Intel e EPC16UC88 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPC20LC20U | EPC16UC88 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | Memory ICs | Memory ICs |
| Status do ciclo de vida | Obsolete | Unknown |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,20 | $0,00 |
| Manufacturer | Altera Corporation (now Intel) | — |
| Função | FPGA Configuration Device (Serial Configuration PROM) | — |
| Tipo de memória | Non-volatile configuration memory | — |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) | — |
| Operating Voltage | 5.0 V (typical) | — |
| Absolute Maximum DC Input | -0.3 V to 7.0 V | — |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) | — |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) | — |
| Contagem de pinos | 20 | — |
| Tipo de montagem | Surface Mount (PLCC socket compatible) | Surface mount |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone | — |
| In-System Programming | Supported via JTAG / Quartus programmer | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Faixa de temperatura de operação | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Status do ciclo de vida | Obsolete / Last-time-buy in distribution | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tensão de alimentação | — | 3.3 V core and I/O |
| Encapsulamento | — | 88-UBGA (11x8) |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Temperatura de operação | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |