EPF10K50EQC240-2 vs EPF10K50VQC240-2 Comparação

Comparação detalhada lado a lado de EPF10K50EQC240-2 por Intel e EPF10K50VQC240-2 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Intel
EPF10K50EQC240-2 EPF10K50EQC240-2 - 50K FLEX-10KE FPGA, 240-PQFP | Intel

EPF10K50EQC240-2 - 50K FLEX-10KE FPGA, 240-PQFP | Intel

EPF10K50EQC240-2 ⚠ Última compra

Comparação de especificações

Parâmetro EPF10K50EQC240-2 EPF10K50VQC240-2
Marca Intel Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Última compra Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $65,00 $28,75
Family FLEX-10KE FLEX 10K
Logic Elements (Cells) 2,880 —
System Gates 50,000 (40,960 typical) —
Logic Array Blocks (LABs) 360 —
Embedded Array Blocks (EABs) 12 —
Total RAM Bits 20,480 bits —
User I/O Pins 189 189
Maximum Operating Frequency 200 MHz —
Core Voltage 2.5 V —
Process Technology 0.22 µm CMOS 0.42 micrometer CMOS, 4-layer metal
Encapsulamento 240-BFQFP / PQFP-240 (34.6 × 34.6 mm, 0.5 mm pitch) 240-BFQFP (240-PQFP / FQFP / QFP-240)
Temperatura de operação 0 °C to +70 °C (Commercial) 0 C to +70 C (Commercial)
Programming Interface IEEE 1149.1 JTAG, Serial EPROM (PS / AS) —
Configuration Memory SRAM (volatile) —
Tipo de montagem Surface Mount (gull-wing leads) Surface Mount
Status RoHS [DATA_NEEDED: rohs status from manufacturer] [DATA_NEEDED: RoHS status - legacy Altera FLEX 10K family typically non-RoHS Pb-bearing BFQFP; verify on distributor listing]
Series — FLEX-10K
Typical Gate Count — 50,000 gates
Logic Elements (LABs) — 360
Logic Cells — 2,880
Embedded Array Memory — 20,480 bits
Number of Terminals — 240
Terminal Form — Gull Wing
Package Code — FQFP
Package Shape — Square
Core Supply Voltage — 3.3 V
I/O Supply Voltage (MultiVolt) — 5.0 V / 3.3 V / 2.5 V
Maximum Internal Frequency — 125 MHz
Propagation Delay (typical) — 0.6 ns
Temperature Grade — Commercial
Configuration Scheme — SRAM-based, serial / parallel via EPC1/EPC2
JTAG / Boundary Scan — IEEE 1149.1 compliant

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