EPM3032ALC44-7 vs EPM3032ALC44-4 Comparação
Comparação detalhada lado a lado de EPM3032ALC44-7 por Altera e EPM3032ALC44-4 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3032ALC44-7 | EPM3032ALC44-4 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $0,95 | $1,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements / Macrocells | 32 macrocells | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| System Gates | 600 | — |
| Number of User I/O Pins | 34 | — |
| Global Clocks | 2 | — |
| Propagation Delay (tPD1, max) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 138.9 MHz | — |
| Supply Voltage (VCCINT / VCCIO) | 3.3 V | — |
| I/O Tolerant Voltage | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Program Memory Type | EEPROM | — |
| In-System Programming (ISP) | Yes - IEEE 1149.1 JTAG | — |
| Temperatura de operação | 0 °C to +70 °C (Commercial) | 0°C to +70°C (Commercial) |
| Encapsulamento | 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height | 44-pin PLCC (J-Lead) |
| Tipo de montagem | Surface Mount | Surface Mount (PLCC J-Lead) |
| Status RoHS | Not Compliant (per Arrow listing) | [DATA_NEEDED: RoHS status] |
| Part Status | Obsolete | — |
| ECCN | EAR99 | — |
| Macrocells | — | 32 |
| User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) |
| Usable Gates | — | 600 to 10,000 (MAX 3000A family range) |
| Technology | — | CMOS EEPROM-based |
| In-System Programmability (ISP) | — | Yes, IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Programming Interface | — | JTAG (ByteBlaster / MasterBlaster) |