EPM3064ATI44-10N vs EPM3064ATC44-7N Comparação
Comparação detalhada lado a lado de EPM3064ATI44-10N por Altera e EPM3064ATC44-7N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3064ATI44-10N | EPM3064ATC44-7N |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $3,95 | $2,30 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | — |
| Usable Gates | 1250 | 1,250 |
| User I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Logic Blocks | 4 | — |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | — |
| Temperatura de operação | -40C to +85C (Industrial, "N" suffix) | 0°C to +85°C (commercial) |
| Encapsulamento | 44-pin TQFP | 44-pin TQFP |
| Process Technology | CMOS EEPROM | — |
| Boundary-Scan Test | Built-in (JTAG) | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | — |
| Status RoHS | Non-Compliant (per digchip datasheet excerpt) | Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 34 |
| Número de pinos | — | 44 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 192.3 MHz (-7 grade) |
| Supply Voltage (VCC) | — | 3.3 V |
| MultiVolt I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| ISP Standard | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test (BST) | — | Built-in, JTAG-driven |