EPM3128ATC100-7 vs EPM3128ATC100-5 Comparação
Comparação detalhada lado a lado de EPM3128ATC100-7 por Intel e EPM3128ATC100-5 por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3128ATC100-7 | EPM3128ATC100-5 |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,20 | $15,43 |
| Family | MAX 3000A | CPLD - MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Typical Gates | 2500 | — |
| User I/Os | 80 | 80 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant inputs | — |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | — |
| ISP Standard | IEEE Std. 1532 (JTAG) | — |
| Encapsulamento | 100-pin TQFP, 14x14 mm, 0.5 mm pitch | 100-pin TQFP (Fine Line) |
| Temperatura de operação | 0C to +70C (Commercial) | 0 °C to 70 °C (Commercial) |
| Speed Grade | -7 (fastest grade in family) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | MAX 3000A |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tpd) | — | 5 ns (commercial); 7.5 ns |
| Maximum Frequency (fCNT) | — | 192.3 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 3.3 V |
| Output Drive Voltage | — | 2.5 V or 3.3 V (programmable) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 compliant |
| JTAG Boundary Scan | — | Yes, IEEE Std. 1149.1 |
| Tipo de montagem | — | Surface Mount |
| Logic Family | — | CMOS |