EPM3128ATI100-10 vs EPM3128ATC100-5N Comparação
Comparação detalhada lado a lado de EPM3128ATI100-10 por Altera e EPM3128ATC100-5N por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3128ATI100-10 | EPM3128ATC100-5N |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,40 | $8,20 |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | Up to 10,000 |
| User I/Os | 80 | 80 |
| Logic Elements / LABs | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V compatible | — |
| Programmability | EEPROM, 3.3 V in-system (JTAG) | — |
| Encapsulamento | TQFP-100 (1.0 mm pitch, 14x14 mm) | TQFP-100 (TC100) |
| Temperatura de operação | -40 °C to +85 °C (industrial) | 0 C to +70 C (commercial) |
| Process Technology | CMOS EEPROM | — |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Boundary-Scan (JTAG) | IEEE 1149.1 compliant | — |
| Status RoHS | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] | [DATA_NEEDED: RoHS compliance] |
| Tipo de montagem | Surface Mount | Surface Mount |
| Device Family | — | MAX 3000A |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| Propagation Delay (tPD) | — | 5 ns |
| Maximum Internal Frequency | — | 192.3 MHz |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |