EPM3512AFI256-7N vs EPM3512AFI256-7 Comparação
Comparação detalhada lado a lado de EPM3512AFI256-7N por Altera e EPM3512AFI256-7 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera
EPM3512AFI256-7N ⚠ Última compraComparação de especificações
| Parâmetro | EPM3512AFI256-7N | EPM3512AFI256-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $27,95 | $15,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Logic Elements / Macrocells | 512 macrocells | — |
| Typical Usable Gates | 10,000 gates | — |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Maximum Operating Frequency (fMAX) | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD, speed grade -7) | approximately 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 2.5 V / 3.3 V / 5 V mixed | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | — |
| Encapsulamento | 256-ball FBGA | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch |
| Faixa de temperatura de operação | -40C to +85C (industrial) | — |
| Lead-Free / RoHS | Yes ('N' suffix, lead-free) | — |
| Design Software | Quartus II (legacy MAX 3000A support) | — |
| Speed Grade | -7 | — |
| Tipo de montagem | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Usable Gates | — | 10,000 |
| User I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| In-System Programmability | — | IEEE Std. 1532 compliant via JTAG |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature (Industrial) | — | -40 °C to +85 °C |
| Status RoHS | — | [DATA_NEEDED: confirm from data] |