EPM3512AQC208-10NS vs EPM3512AQC208-10-10N Comparação
Comparação detalhada lado a lado de EPM3512AQC208-10NS por Altera e EPM3512AQC208-10-10N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N ObsoleteComparação de especificações
| Parâmetro | EPM3512AQC208-10NS | EPM3512AQC208-10-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $32,40 | $31,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/Os | 172 | 172 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 2.5 V / 3.3 V / 5.0 V |
| Logic Family | CMOS, EEPROM-based | — |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Encapsulamento | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Temperatura de operação | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| Status RoHS | [DATA_NEEDED: rohs status] | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Macrocells | — | 512 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Maximum Frequency (fCNT) | — | 87 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 compliant |
| Boundary-Scan (JTAG) | — | Yes, IEEE 1149.1 |
| PCI-SIG Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS status] |