EPM3512AQC208-3N vs EPM3512AQC208-10S Comparação
Comparação detalhada lado a lado de EPM3512AQC208-3N por Altera e EPM3512AQC208-10S por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3512AQC208-3N | EPM3512AQC208-10S |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $16,40 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Macrocells per LAB | 32 | — |
| Pin-to-Pin Logic Delay | 3 ns (speed grade -3) | — |
| Global Clock Setup Time | [DATA_NEEDED: actual tSU at 3 ns grade] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) | — |
| Temperatura de operação | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulamento | PQFP-208 | 208-pin FineLine BGA-256 |
| Tipo de montagem | Surface Mount | — |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | CMOS EEPROM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Status RoHS | [DATA_NEEDED: not stated in retrieved snippets] | [DATA_NEEDED: rohs_status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1750 |
| User I/Os | — | 208 |
| Speed Grade | — | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |
| Process Technology | — | EEPROM-based CMOS |