EPM5192AGC84-20 vs EPM5192AJC-25 Comparação
Comparação detalhada lado a lado de EPM5192AGC84-20 por Altera e EPM5192AJC-25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM5192AGC84-20 | EPM5192AJC-25 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $41,20 | $8,20 |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 EPLD |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| Encapsulamento | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | PLCC-68 (windowed ceramic, AJC) |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | UV-erasable (windowed ceramic package) |
| Process Technology | CMOS | — |
| Operating Temperature Grade | Commercial | — |
| Tensão de alimentação | [DATA_NEEDED: VCC range] | 5 V (typical) |
| I/O Standard | 5V CMOS / TTL compatible | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Tipo de montagem | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Manufacturer | — | Altera (now Intel PSG) |
| Propagation Delay (tPD) | — | 25 ns |
| Contagem de pinos | — | 68 |
| Logic Blocks | — | MAX 5000 LABs (Logic Array Blocks) |
| Programmable Pins | — | [DATA_NEEDED: number of user I/O pins] |
| Temperatura de operação | — | [DATA_NEEDED: exact operating temperature range] |
| Programming Technology | — | EPROM (non-volatile) |
| Military Grade | — | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) |